4
FN8195.1
April 26, 2006
PIN NAMES
PRINCIPLES OF OPERATION
The X9420 is a highly integrated microcircuit
incorporating a resistor array and associated registers
and counter and the serial interface logic providing
direct communication between the host and the XDCP
potentiometer.
Serial Interface
The X9420 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS
must be
LOW and the HOLD
and WP pins must be HIGH
during the entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
Array Description
The X9420 is comprised of one resistor array
containing 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (V
H
/R
H
and V
L
/R
L
inputs).
At both ends of the array and between each resistor
segment is a CMOS switch connected to the wiper
(V
W
/R
W
) output. Within the individual array only one
switch may be turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The six bits of the WCR are decoded to
select, and enable, one of sixty-four switches. The block
diagram of the potentiometer is shown in Figure 1.
Wiper Counter Register (WCR)
The X9420 contains a Wiper Counter Register. The
WCR can be envisioned as a 6-bit parallel and serial
load counter with its outputs decoded to select one of
sixty-four switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated data registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/ Decrement
instruction. Finally, it is loaded with the contents of its
data register zero (DR0) upon power-up.
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9420 is powered-
down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
Data Registers
The potentiometer has four 6-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the WCR. It should be noted all
operations changing data in one of the Data Registers is
a nonvolatile operation and will take a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
Register Descriptions
Table 1. Data Registers, (6-bit), Nonvolatile
There are four 6-bit Data Registers associated with the
potentiometer.
{D5~D0}: These bits are for general purpose Non-
volatile data storage or for storage of up to four dif-
ferent wiper values.
Table 2. Wiper Counter Register, (6-bit), Volatile
{WP5~WP0}: These bits specify the wiper position
of the potentiometer.
Symbol Description
SCK Serial Clock
SI, SO Serial Data
A0 Device Address
V
H
/R
H
,
V
L
/R
L
Potentiometer Pins (terminal equivalent)
V
W
/R
W
Potentiometer Pins (wiper equivalent)
WP Hardware Write Protection
HOLD Serial Communication Pause
V+,V- Analog Supplies
V
CC
System Supply Voltage
V
SS
System Ground
NC No Connection
0 0 D5 D4 D3 D2 D1 D0
(MSB) (LSB)
0 0 WP5 WP4 WP3 WP2 WP1 WP0
(MSB) (LSB)
X9420
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FN8195.1
April 26, 2006
Figure 1. Detailed Potentiometer Block Diagram
Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the CS
pin goes from LOW to
HIGH after a complete write sequence is received by
the device. The progress of this internal write operation
can be monitored by a Write In Process bit (WIP). The
WIP bit is read with a Read Status command.
INSTRUCTIONS
Address/Identification (ID) Byte
The first byte sent to the X9420 from the host,
following a CS
going HIGH to LOW, is called the
Address or Identification byte. The most significant
four bits of the slave address are a device type
identifier, for the X9420 this is fixed as 0101[B] (refer
to Figure 2).
The least significant bit in the ID byte selects one of
two devices on the bus. The physical device address
is defined by the state of the A
0
input pin. The X9420
compares the serial data stream with the address
input state; a successful compare of the address bit is
required for the X9420 to successfully continue the
command sequence. The A
0
input can be actively
driven by a CMOS input signal or tied to V
CC
or V
SS
.
The remaining three bits in the ID byte must be set to 110.
Figure 2. Address/Identification Byte Format
Instruction Byte
The next byte sent to the X9420 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next two
bits point to one of four data registers. The format is
shown below in Figure 3.
Figure 3. Instruction Byte Format
Serial Data Path
From Interface
Circuitry
Register 0 Register 1
REGISTER 2 REGISTER 3
Serial
Bus
Input
Parallel
Bus
Input
Counter
Register
INC/DEC
Logic
UP/DN
CLK
Modified SCK
UP/DN
V
H
V
L
V
W
8 6
C
O
U
N
T
E
R
D
E
C
O
D
E
IF WCR = 00[H] THEN V
W
= V
L
IF WCR = 3F[H] THEN V
W
= V
H
Wiper
(WCR)
100
11 0A0
Device Type
Identifier
Device Address
1
I1I2I3 I0 R1 R0 0 0
Register
Select
Instructions
X9420
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FN8195.1
April 26, 2006
The four high order bits of the instruction byte specify
the operation. The next two bits (R
1
and R
0
) select
one of the four registers that is to be acted upon when
a register oriented instruction is issued. The last two
bits are defined as 0.
Two of the eight instructions are two bytes in length
and end with the transmission of the instruction byte.
These instructions are:
XFR Data Register to Wiper Counter Register
This instruction transfers the contents of one speci-
fied Data Register to the Wiper Counter Register.
XFR Wiper Counter Register to Data Register
—This
instruction transfers the contents of the Wiper
Counter Register to the specified associated Data
Register.
The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the wiper
to this action will be delayed by t
WRL
. A transfer from
the WCR (current wiper position), to a Data Register is
a write to nonvolatile memory and takes a minimum of
t
WR
to complete. The transfer can occur between the
potentiometer and one of its associated registers.
Five instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9420; either between the host and
one of the Data Registers or directly between the host
and the WCR. These instructions are:
Read Wiper Counter Register
—read the current
wiper position of the pot,
Write Wiper Counter Register
—change current
wiper position of the pot,
Read Data Register
—read the contents of the
selected data register;
Write Data Register
—write a new value to the
selected data register.
Read Status
—This command returns the contents
of the WIP bit which indicates if the internal write
cycle is in progress.
The sequence of these operations is shown in Figure
5 and Figure 6.
The final command is Increment/Decrement. It is
different from the other commands, because it’s length
is indeterminate. Once the command is issued, the
master can clock the wiper up and/or down in one
resistor segment steps; thereby, providing a fine
tuning capability to the host. For each SCK clock pulse
(t
HIGH
) while SI is HIGH, the selected wiper will move
one resistor segment towards the V
H
/R
H
terminal.
Similarly, for each SCK clock pulse while SI is LOW,
the selected wiper will move one resistor segment
towards the V
L
/R
L
terminal. A detailed illustration of
the sequence and timing for this operation are shown
in Figure 7 and Figure 8.
Figure 4. Two-Byte Instruction Sequence
0101110A0I3 I2 I1 I0 R1 R0 0 0
SCK
SI
CS
X9420

X9420WS16

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
IC DIGITAL POT 10K 64TP 16SOIC
Lifecycle:
New from this manufacturer.
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