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X9420WS16I-2.7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
7
FN8195.1
April 26, 2006
Figure 5. Three-Byte Instruction Sequence (Write)
Figure 6. Three-Byte Instruction Sequence (Read)
Figure 7. Increment/Decrement Instruction Sequence
Figure 8. Increment/Decrement Timing Limits
0 101 0A0 I3 I2 I1 I0 R1 R0 0 0
SCL
SI
0 0 D5 D4 D3 D2 D1 D0
CS
11
0 101 0A0 I3 I2 I1 I0 R1 R0 0 0
SCL
SI
CS
11
S0
0 0 D5 D4 D3 D2 D1 D0
Don’t Care
0101110A0 I3 I2 I1 I0 0 0 0
SCK
SI
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
0
CS
SCK
SI
V
W
INC/DEC CMD Issued
t
WRID
Voltage Out
X9420
8
FN8195.1
April 26, 2006
Table 3. Instruction Set
Instruction
Instruction Set
OperationI
3
I
2
I
1
I
0
R
1
R
0
Read Wiper Counter
Register
1 0 0 1 0 0 0 0 Read the contents of the Wiper Counter Register
Write Wiper Counter
Register
1 0 1 0 0 0 0 0 Write new value to the Wiper Counter Register
Read Data Register 1 0 1 1 R
1
R
0
0 0 Read the contents of the Data Register pointed to by
R
1
- R
0
Write Data Register 1 1 0 0 R
1
R
0
0 0 Write new value to the Data Register pointed to by
R
1
- R
0
XFR Data Register to
Wiper Counter
Register
1101R
1
R
0
0 0 Transfer the contents of the Data Register pointed to
by R
1
- R
0
to the Wiper Counter Register
XFR Wiper Counter
Register to Data
Register
1110R
1
R
0
0 0 Transfer the contents of the Wiper Counter
Register to the Data Register pointed to by R
1
- R
0
Increment/Decrement
Wiper Counter
Register
0 0 1 0 0 0 0 0 Enable Increment/decrement of the Wiper Counter
Register
Read Status (WIP bit) 0 1 0 1 0 0 0 1 Read the status of the internal write cycle, by check-
ing the WIP bit.
X9420
9
FN8195.1
April 26, 2006
Instruction Format
Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master.
(2) WPx refers to wiper position data in the Wiper Counter Register
“I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
(3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
Read Wiper Counter Register (WCR)
Write Wiper Counter Register (WCR)
Read Data Register (DR)
Read the contents of the Register pointed to by R1 - R0.
Write Data Register (DR)
Write a new value to the Register pointed to by R1 - R0.
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Transfer the contents of the Register pointed to by R1 - R0 to the WCR.
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
wiper position
(sent by X9420 on SO)
CS
Rising
Edge
0101110
A
0
1001000000
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
Data Byte
(sent by Host on SI)
CS
Rising
Edge
0101110
A
0
1010000000
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
register
addresses
Data Byte
(sent by X9420 on SO)
CS
Rising
Edge
0101110
A
0
1011
R
1
R
0
0000
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
register
addresses
Data Byte
(sent by host on SI)
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
0101110
A
0
1100
R
1
R
0
0000
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
register
addresses
CS
Rising
Edge
0101110
A
0
1101
R
1
R
0
00
X9420
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

X9420WS16I-2.7

Mfr. #:
Buy X9420WS16I-2.7
Manufacturer:
Renesas / Intersil
Description:
IC DIGITAL POT 10K 64TP 16SOIC
Lifecycle:
New from this manufacturer.
Delivery:
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