LTC1063
7
1063fa
PI FU CTIO S
U
UU
Power Supply Pins (Pins 6, 3, N Package)
The positive and negative supply pin should be bypassed
with a high quality 0.1µF ceramic capacitor. In applications
where the clock pin (5) is externally swept to provide
several cutoff frequencies, the output DC offset variation
is minimized by connecting an additional 1µF solid tanta-
lum capacitor in parallel with the 0.1µF disc ceramic. This
technique was used to generate the graphs of the output
DC offset variation versus clock; they are illustrated in the
Typical Performance Characteristics section.
When the power supply voltage exceeds ±7V, and when V
–
is applied before V
+
, if V
+
is allowed to go below ground,
connect a signal diode between the positive supply pin and
ground to prevent latch-up (see Typical Applications).
Ground Pin (Pin 2, N Package)
The ground pin merges the internal analog and digital
ground paths. The potential of the ground pin is the
reference for the internal switched-capacitor resistors,
and the reference for the external clock. The positive input
of the internal op amp is also tied to the ground pin.
For dual supply operation, the ground pin should be
connected to a high quality AC and DC ground. A ground
plane, if possible, should be used. A poor ground will
degrade DC offset and it will increase clock feedthrough,
noise and distortion.
A small amount of AC current flows out of the ground pin
whether or not the internal oscillator is used. The fre-
quency of the ground current equals the frequency of the
internal or external clock. The average value of this current
is approximately 55µA, 110µA, 170µA for ±2.5V, ±5V and
±7.5V supplies respectively.
For single supply operation, the ground pin should be
preferably biased at half supply (see Typical Applications).
V
OS
Adjust Pin (Pin 8, N Package)
The V
OS
adjust pin can be used to trim any small amount
of output DC offset voltage or to introduce a desired output
DC level. The DC gain from the V
OS
adjust pin to the filter
output pin equals two.
Any DC voltage applied to this pin will reflect at the output
pin of the filter multiplied by two.
If the V
OS
adjust pin is not used, it should be shorted to the
ground pin. The DC bias current flowing into the V
OS
adjust
pin is typically 10pA.
Pin 8 should always be connected to an AC ground; AC
signals applied to this pin will degrade the filter response.
Input Pin (Pin 1, N Package)
Pin 1 is the filter input and it is connected to an internal
switched-capacitor resistor. If the input pin is left floating,
the filter output will saturate. The DC input impedance of
pin 1 is very high; with ±5V supplies and 1MHz clock, the
DC input impedance is typically 1GΩ. A resistor, R
IN
, in
series, with the input pin will not alter the value of the
filter’s DC output offset (Figure 1). R
IN
should, however,
be limited to a maximum value (Table 1), otherwise the
filter’s passband flatness will be affected. Refer to the
Applications Information section for more details.
V
IN
V
OUT
1063 F01
V
–
V
+
R
IN
1
2
3
4
8
7
6
5
LTC1063
f
CLK
Table 1. R
IN(MAX)
vs Clock and Power Supply
R
IN(MAX)
V
S
= ±7.5V V
S
= ±5V V
S
= ±2.5V
f
CLK
= 4MHz 2.2k – –
f
CLK
= 3MHz 3.4k 2.9k –
f
CLK
= 2MHz 5.5k 5k 2.7k
f
CLK
= 1MHz 11k 11k 9.2k
f
CLK
= 500kHz 24k 23k 21k
f
CLK
= 100kHz 120k 120k 110k
Figure 1.
