MT8814 Data Sheet
3
Zarlink Semiconductor Inc.
Functional Description
The MT8814 is an analog switch matrix with an array size of 8 x 12. The switch array is arranged such that there
are 8 columns by 12 rows. The columns are referred to as the Y inputs/outputs and the rows are the X
inputs/outputs. The crosspoint analog switch array will interconnect any X I/O with any Y I/O when turned on and
provide a high degree of isolation when turned off. The control memory consists of a 96 bit write only RAM in which
the bits are selected by the address inputs (AY0-AY2, AX0-AX3). Data is presented to the memory on the DATA
input. Data is asynchronously written into memory whenever both the CS (Chip Select) and STROBE inputs are
high and are latched on the falling edge of STROBE. A logical “1” written into a memory cell turns the
corresponding crosspoint switch on and a logical “0” turns the crosspoint off. Only the crosspoint switches
corresponding to the addressed memory location are altered when data is written into memory. The remaining
switches retain their previous states. Any combination of X and Y inputs/outputs can be interconnected by
establishing appropriate patterns in the control memory. A logical “1” on the RESET input will asynchronously return
all memory locations to logical “0” turning off all crosspoint switches regardless of whether CS is high or low.
Two voltage reference pins (V
SS
and V
EE
) are provided for the MT8814 to enable switching of negative analog
signals. The range for digital signals is from V
DD
to V
SS
while the range for analog signals is from V
DD
to V
EE
. V
SS
and V
EE
pins can be tied together if a single voltage reference is needed.
Address Decode
The seven address inputs along with the STROBE and CS (Chip Select) are logically ANDed to form an enable
signal for the resettable transparent latches. The DATA input is buffered and is used as the input to all latches. To
write to a location, RESET must be low and CS must go high while the address and data are set up. Then the
STROBE input is set high and then low causing the data to be latched. The data can be changed while STROBE is
high, however, the corresponding switch will turn on and off in accordance with the DATA input. DATA must be
stable on the falling edge of STROBE in order for correct data to be written to the latch.
19 21 Y5 Y5 Analog (Input/Output): this is connected to the Y5 column of the switch
array.
20 22 V
EE
Negative Power Supply.
21 23 Y4 Y4 Analog (Input/Output): this is connected to the Y4 column of the switch
array.
22, 23 24,25 AX1,AX2 X1 and X2 Address Lines (Inputs).
24, 25 26,27 AY0,AY1 Y0 and Y1 Address Lines (Inputs).
26, 27 28-31 NC No Connection.
28 - 33 32-37 X5-X0 X5-X0 Analog (Inputs/Outputs): these are connected to the X5-X0 rows of the
switch array.
34 38 NC No Connection.
35 39 Y0 Y0 Analog (Input/Output): this is connected to the Y0 column of the switch
array.
36 40 CS Chip Select (Input): this is used to select the device. Active High.
37 41 Y1 Y1 Analog (Input/Output): this is connected to the Y1 column of the switch
array.
38 42 DATA DATA (Input): a logic high input will turn on the selected switch and a logic low
will turn off the selected switch. Active High.
39 43 Y2 Y2 Analog (Input/Output): this is connected to the Y2 column of the switch
array.
40 44 V
DD
Positive Power Supply.
Pin Description
Pin #
Name Description
PDIP PLCC
