IDT82V3398 PRODUCT BRIEF SYNCHRONOUS ETHERNET WAN PLL AND CLOCK GENERATION FOR IEEE-1588
Pin Description 6 August 1, 2012
IN5 39
I
pull-down
CMOS
IN5: Input Clock 5
A 1PPS, 2 kHz, 4 kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz, 6.48
MHz, 10 MHz, 19.44 MHz, 25 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52
MHz or 156.25 MHz clock is input on this pin.
IN6 40
I
pull-down
CMOS
IN6: Input Clock 6
A 1PPS, 2 kHz, 4 kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz, 6.48
MHz, 10 MHz, 19.44 MHz, 25 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52
MHz or 156.25 MHz clock is input on this pin.
Output Frame Synchronization Signal
FRSYNC_8K_1P
PS
19 O CMOS
FRSYNC_8K_1PPS: 8 kHz Frame Sync Output
An 8 kHz signal or a 1PPS sync signal is output on this pin.
MFRSYNC_2K_
1PPS
20 O CMOS
MFRSYNC_2K_1PPS: 2 kHz Multiframe Sync Output
A 2 kHz signal or a 1PPS sync signal is output on this pin.
Output Clock
OUT1
OUT2
OUT3
OUT4
62
63
64
67
OCMOS
OUT1 ~ OUT4: Output Clock 1 ~ 4
A 1PPS, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1
4
, N x T1
5
, N x 13.0 MHz
6
, N x 3.84 MHz
7
,
5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,
77.76 MHz, 25MHz, 25.78125 MHz, 125 MHz, 128.90625 MHz, 155.52 MHz or 156.25 MHz
or 161.1328125 MHz clock is output on these pins.
OUT5_POS
OUT5_NEG
25
26
O PECL/LVDS
OUT5_POS / OUT5_NEG: Positive / Negative Output Clock 5
A 1PPS, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1
4
, N x T1
5
, N x 13.0 MHz
6
, N x 3.84 MHz
7
,
5 MHz, 10 MHz, 20 MHz, 25 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz,
51.84 MHz, 77.76 MHz, 125 MHz, 128.90625 MHz, 155.52 MHz, 156.25 MHz, 161.1328125
MHz, 311.04 MHz, 312.5 MHz, 322.265625 MHz, 622.08 MHz, 625 MHz or 644.53125 MHz
clock is differentially output on these pair of pins.
OUT6_POS
OUT6_NEG
23
24
O PECL/LVDS
OUT6_POS / OUT6_NEG: Positive / Negative Output Clock 6
A 1PPS, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1
4
, N x T1
5
, N x 13.0 MHz
6
, N x 3.84 MHz
7
,
5 MHz, 10 MHz, 20 MHz, 25 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz,
51.84 MHz, 77.76 MHz, 125 MHz, 128.90625 MHz, 155.52 MHz, 156.25 MHz, 161.1328125
MHz, 311.04 MHz, 312.5 MHz, 322.265625 MHz, 622.08 MHz, 625 MHz or 644.53125MHz
clock is differentially output on these pair of pins.
VC 2 O Analog
VC: This pin must be connected to ground.
VC0 16 O Analog
VC0: APLL VC Output
External RC filter
See “APLL” on page 35 for details.
Lock Signal
DPLL_LOCK
42 O CMOS
DPLL_LOCK
This pin goes high when DPLL is locked
Microprocessor Interface
CS / I2C_AD0 51
I/O
pull-up
CMOS
CS: Chip Selection
In Serial mode, this pin is an input.A transition from high to low must occur on this pin for
each read or write operation and this pin should remain low until the operation is over.
I2C_AD0: Device Address Bit 0
In I2C mode, I2C_AD[2:0] pins are the address bus of the microprocessor interface.
INT_REQ 5 O CMOS
INT_REQ: Interrupt Request
This pin is used as an interrupt request. The output characteristics are determined by the
HZ_EN bit (b1, 0CH) and the INT_POL bit (b0, 0CH).
Table 1: Pin Description (Continued)
Name Pin No. I/O Type
Description
1, 2