4
FN8202.1
July 28, 2006
Absolute Maximum Ratings Recommended Operating Conditions
Junction Temperature under bias. . . . . . . . . . . . . . .-65°C to +135°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage at any digital interface pin
with respect to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V
V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V
Voltage at any DCP pin with
respect to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to V
CC
Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . .300°C
I
W
(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage (V
CC
) (Note 4) Limits . . . . . . . . . . . . . . 2.7V to 5.5V
CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation
of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Analog Specifications Over recommended operating conditions unless otherwise stated.
SYMBOL PARAMETER TEST CONDITIONS MIN
TYP
(Note 4) MAX UNIT
R
TOTAL
End to end resistance Y, W, U, T versions respectively 2.8, 10, 50,
100
kΩ
End to end resistance tolerance -20 +20 %
Power rating 25C, each DCP 50 mW
R
TOTAL
Matching
DCP to DCP resistance matching 0.75 2.0 %
I
W
(Note 5) Wiper current See test circuit -3.0 +3.0 mA
R
W
Wiper resistance
Wiper current =
50 150 Ω
V
TERM
Voltage on any DCP pin Vss Vcc V
Noise (Note 5) Ref: 1kHz -120 dBV
Resolution 0.4 %
Absolute linearity (Note 1) V(R
H0
)=V(R
H1
)=V
CC
V(R
L0
)=V(R
L1
)=V
SS
-1 +1 MI (Note 3)
Relative linearity
(Note 2) -0.3 +0.3 MI (Note 3)
Temperature coefficient of resistance
(Note 5)
±300 ppm/°C
Ratiometric Temperature (Note 5)
Coefficient
-20 +20 ppm/C
C
H
/C
L
/C
W
Potentiometer Capacitance (Note 5) See equivalent circuit 10/10/25 pF
I
OL
Leakage on DCP pins Voltage at pin from V
SS
to V
CC
0.1 10 µA
V
CC
R
TOTAL
DC Electrical Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNITS
I
CC1
V
CC
supply current (Volatile write/read) f
SCL
= 400kHz; SDA = Open; (for 2-Wire, Active,
Read and Volatile Write States only)
3mA
I
CC2
V
CC
supply current (active) f
SCL
= 200kHz; (for U/D interface, increment,
decrement)
3mA
I
CC3
V
CC
supply current (nonvolatile write) f
SCL
= 400kHz; SDA = Open;
(for 2-Wire, Active, Nonvolatile Write State only)
5mA
I
SB
V
CC
current (standby) V
CC
= +5.5V; V
IN
= V
SS
or V
CC
; SDA = V
CC
;
(for 2-Wire, Standby State only)
20 µA
I
L
Leakage current, bus interface pins Voltage at pin from V
SS
to V
CC
-10 10 µA
X9455
5
FN8202.1
July 28, 2006
V
IH
Input HIGH voltage V
CC
x 0.7 V
CC
+ 1 V
V
IL
Input LOW voltage -1 V
CC
x 0.3 V
V
OL
SDA pin output LOW voltage I
OL
= 3mA 0.4 V
DC Electrical Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNITS
Endurance and Data Retention
PARAMETER MIN UNITS
Minimum endurance 100,000 Data changes per bit
Data retention 100 Years
Capacitance
SYMBOL TEST TEST CONDITIONS MAX UNITS
C
IN/OUT
(Note 5) Input / Output capacitance (SDA) V
OUT
= 0V 8 pF
C
IN
(Note 5) Input capacitance (DS0, DS1, CS, U/D, SCL, WP, A2, A1
and A0
)
V
IN
= 0V 6 pF
Power-Up Timing
SYMBOL PARAMETER MAX UNITS
t
D
(Notes 5, 9) Power Up Delay from V
CC
power up (V
CC
above 2.7V) to wiper position recall
completed, and communication interfaces ready for operation.
2ms
A.C. Test Conditions
Input Pulse Levels V
CC
x 0.1 to V
CC
x 0.9
Input rise and fall times 10ns
Input and output timing threshold level V
CC
x 0.5
External load at pin SDA 2.3kΩ to V
CC
and 100 pF to V
SS
2-Wire Interface Timing (s)
SYMBOL PARAMETER MIN MAX UNITS
f
SCL
Clock Frequency 400 kHz
t
HIGH
Clock High Time 600 ns
t
LOW
Clock Low Time 1300 ns
t
SU:STA
Start Condition Setup Time 600 ns
t
HD:STA
Start Condition Hold Time 600 ns
t
SU:STO
Stop Condition Setup Time 600 ns
t
SU:DAT
SDA Data Input Setup Time 100 ns
t
HD:DAT
SDA Data Input Hold Time 30 ns
t
R
(Note 5) SCL and SDA Rise Time 300 ns
t
F
(Note 5) SCL and SDA Fall Time 300 ns
t
AA
(Note 5) SCL Low to SDA Data Output Valid Time 0.9 µs
t
DH
SDA Data Output Hold Time 0 ns
t
IN
(Note 5) Pulse Width Suppression Time at SCL and SDA inputs 50 ns
t
BUF
(Note 5) Bus Free Time (Prior to Any Transmission) 1200 ns
X9455
6
FN8202.1
July 28, 2006
SDA vs. SCL Timing
WP
, A0, A1, and A2 Pin Timing
t
SU:WPA
(Note 5)
A0, A1, A2 and WP Setup Time 600 ns
t
HD:WPA
(Note 5)
A0, A1, A2 and WP Hold Time 600 ns
2-Wire Interface Timing (s) (Continued)
SYMBOL PARAMETER MIN MAX UNITS
t
SU:STO
t
DH
t
HIGH
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
SCL
SDA
(Input Timing)
SDA
(Output Timing)
t
F
t
LOW
t
BUF
t
AA
t
R
t
HD:WP
SCL
SDA IN
WP, A0, A1, or A2
t
SU:WP
Clk 1
START
STOP
Increment/Decrement Timing
SYMBOL PARAMETER MIN TYP
(Note 4) MAX UNITS
t
CI
CS to SCL Setup 600 ns
t
ID
(Note 5) SCL HIGH to U/D, DS0 or DS1 change 600 ns
t
DI
(Note 5) U/D, DS0 or DS1 to SCL setup 600 ns
t
IL
SCL LOW period 2.5 µs
t
IH
SCL HIGH period 2.5 µs
t
IC
SCL inactive to CS inactive (Nonvolatile Store Setup Time) 1 µs
t
CPHS
CS deselect time (STORE) 10 ms
t
CPHNS
(Note 5)
CS deselect time (NO STORE) 1 µs
t
IW
(Note 5) SCL to R
W
change 100 500 µs
t
CYC
SCL cycle time 5 µs
t
R
, t
F
(Note 5) SCL input rise and fall time 500 µs
X9455

X9455UV24I-2.7

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
IC DCP DUAL 50K 256TAP 24-TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
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