1. Description
The Atmel
®
ATmega324PB is a low-power CMOS 8-bit microcontroller based on the AVR enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega324PB achieves
throughputs close to 1MIPS per MHz. This empowers system designer to optimize the device for power
consumption versus processing speed.
The Atmel AVR
®
core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers
to be accessed in a single instruction executed in one clock cycle. The resulting architecture is more code
efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega324PB provides the following features: 32K bytes of In-System Programmable Flash with
Read-While-Write capabilities, 1Kbytes EEPROM, 2Kbytes SRAM, 39 general purpose I/O lines, 32
general purpose working registers, five flexible Timer/Counters with compare modes, internal and
external interrupts, three serial programmable USART, two byte-oriented 2-wire Serial Interface (I2C), two
SPI serial port, a 8-channel 10-bit ADC with optional differential input stage with programmable gain, a
programmable Watchdog Timer with internal Oscillator, IEEE std. 1149.1 compliant JTAG test interface,
also used for accessing the On-chip Debug system and programming, Clock failure detection mechanism
and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM,
Timer/Counters, USART, 2-wire Serial Interface, SPI port, and interrupt system to continue functioning.
PTC with enabling up to 32 self-cap and 256 mutual-cap sensors. The Power-down mode saves the
register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or
hardware reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to
maintain a timer base while the rest of the device is sleeping. Also ability to run PTC in power-save mode/
wake-up on touch and Dynamic on/off of PTC analog and digital portion. The ADC Noise Reduction mode
stops the CPU and all I/O modules except asynchronous timer, PTC, and ADC to minimize switching
noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest
of the device is sleeping. This allows very fast start-up combined with low power consumption.
Atmel offers the QTouch
®
library for embedding capacitive touch buttons, sliders and wheels functionality
into AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and
includes fully debounced reporting of touch keys and includes Adjacent Key Suppression
®
(AKS
®
)
technology for unambiguous detection of key events. The easy-to-use QTouch Composer allows you to
explore, develop and debug your own touch applications.
The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP
Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a
conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core.
The Boot program can use any interface to download the application program in the Application Flash
memory. Software in the Boot Flash section will continue to run while the Application Flash section is
updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System
Self-Programmable Flash on a monolithic chip, the Atmel ATmega324PB is a powerful microcontroller
that provides a highly flexible and cost effective solution to many embedded control applications.
The ATmega324PB is supported with a full suite of program and system development tools including: C
Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.
Atmel ATmega324PB [DATASHEET]
Atmel-42546C-ATmega324PB_Datasheet_Summary-10/2016
4
