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ATMEGA169L-8MI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
19
ATmega169V/L
2514HS–AVR–05/03
Data Sheet Change
Log for ATmega169
Please note that the referring page numbers in this section are referred to this docu-
ment. The referring revision in this section are referring to the document revision.
Changes from Rev.
2514A-08/02 to Rev.
2514B-09/02
1. Canged the Endurance on the Flash to 10,000 Write/Erase Cycles.
Changes from Rev.
2514B-09/02 to Rev.
2514C-11/02
1. Added “Errata” on page 17.
2. Added Information for the 64-pad MLF Package in “Ordering Information” on
page 14 and “Packaging Information” on page 15.
3. Changed Temerature Range and Removed Industrial Ordering Codes in
“Packaging Information” on page 15.
Changes from Rev.
2514C-11/02 to Rev.
2514D-01/03
1. Added TCK frequency limit in “Programming via the JTAG Interface” on page
284.
2. Added Chip Erase as a first step in “Programming the Flash” on page 294 and
“Programming the EEPROM” on page 295.
3. Added the section “Unconnected Pins” on page 56.
4. Added tips on how to disable the OCD system in “On-chip Debug System” on
page 35.
5. Corrected interrupt addresses. ADC and ANA_COMP had swapped places.
6. Improved the table in “SPI Timing Characteristics” on page 299 and removed
the table in “SPI Serial Programming Characteristics” on page 284.
7. Changed “will be ignored” to “must be written to zero” for unused Z-pointer
bits in “Performing a Page Write” on page 260.
8. Corrected “LCD Frame Complete” to “LCD Start of Frame” in the LCDCRA
Register description on page 220.
9. Changed OUT to STS and IN to LDS in USI code examples, and corrected
f
SCKmax
. The USI I/O Registers are in the extended I/O space, so IN and OUT
cannot be used. LDS and STS take one more cycle when executed, so f
SCKmax
had to be changed accordingly.
10. Removed TOSKON and TOSCK from Table 103 on page 239, and g10 and g20
from Figure 114 on page 241 and Table 105 on page 242, because these sig-
nals do not exist in boundary scan.
11. Changed from 4 to 16 MIPS and MHz in the device Features list.
12. Corrected Port A to Port F in “AVCC” on page 6 under “Pin Descriptions” on
page 5.
20
ATmega169V/L
2514HS–AVR–05/03
13. Corrected 230.4 Mbps to 230.4 kbps in “Examples of Baud Rate Setting” on
page 174.
14. Corrected placing of falling and rising XCK edges in Table 78, “UCPOL Bit
Settings,” on page 173.
15. Removed reference to Multipurpose Oscillator Application Note, which does
not exist.
16. Corrected Number of Calibrated RC Oscillator Cycles in Table 1 on page 19
from 8,448 to 67,584.
17. Various minor Timer1 corrections.
18. Added information about PWM symmetry for Timer0 and Timer2.
19. Corrected the contents of DIDR0 and DIDR1.
20. Made all bit names in the LCDDR Registers unique by adding the COM num-
ber digit in front of the two digits already there, e.g. SEG304.
21. Changed Extended Standby to ADC Noise Reduction mode under “Asynchro-
nous Operation of Timer/Counter2” on page 139.
22. Added note about Port B having better driving capabilities than the other
ports. As a consequence the table, “DC Characteristics” on page 297 was cor-
rected as well.
23. Added note under “Filling the Temporary Buffer (Page Loading)” on page 260
about writing to the EEPROM during an SPM page load.
24. Removed ADHSM completely.
25. Updated “Packaging Information” on page 15.
Changes from Rev.
2514D-01/03 to Rev.
2514E-02/03
1. Updated the section “Features” on page 1 with information regarding
ATmega169 and ATmega169L.
2. Removed all references to the PG5 pin in Figure 1 on page 2, Figure 2 on page
3, “Port G (PG4..PG0)” on page 6, “Alternate Functions of Port G” on page 71,
and “Register Description for I/O-Ports” on page 73.
3. Updated Table 118, “Extended Fuse Byte,” on page 267.
4. Added Errata for “ATmega169 Rev C” on page 18, including “Significan Data
Sheet Changes”.
5. Updated the “Ordering Information” on page 14 to include the new speed
grade for ATmega169L and the new 16 MHz ATmega169.
21
ATmega169V/L
2514HS–AVR–05/03
Changes from Rev.
2514E-02/03 to Rev.
2514F-04/03
1. Renamed ICP to ICP1 in whole document.
2. Removed note on “Crystal Oscillator Operating Modes” on page 25.
3. XTAL1/XTAL2 can be used as timer oscillator pins, described in chapter “Cal-
ibrated Internal RC Oscillator” on page 27.
4. Switching between prescaler settings in “Switching Time” on page 31.
5. Updated DC and ACD Characteristics in chapter “Electrical Characteristics”
on page 297 are updated. Removed TBDs from Table 16 on page 37, Table 19
on page 41, Table 133 on page 299.
6. Updated Figure 22 on page 52, Figure 25 on page 57 and Figure 109 on page
238 regarding WRITE PINx REGISTER.
7. Updated “Alternate Functions of Port F” on page 69 regarding JTAG.
8. Replaced Timer0 Overflow with Timer/Counter0 Compare Match in “Universal
Serial Interface – USI” on page 178. Also updated “Start Condition Detector”
on page 184 and “USI Control Register – USICR” on page 186.
9. Updated Features for “Analog to Digital Converter” on page 192 and Table 88
on page 205.
10. Added notes on Figure 117 on page 259 and Table 118 on page 267.
Changes from Rev.
2514F-04/03 to Rev.
2514G-04/03
1. Updated “ATmega169 Typical Characteristics – Preliminary Data” on page
303.
2. Updated typo in “Ordering Information” on page 14.
3. Updated Figure 45 on page 109, Table 18 on page 39, and Table 100 on page
233.
Changes from Rev.
2514G-04/03 to Rev.
2514H-05/03
1. Updated typo in Figure 145, Figure 165, and Figure 192.
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ATMEGA169L-8MI

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