Data Sheet ADF4156
Rev. E | Page 17 of 24
RF SYNTHESIZER: A WORKED EXAMPLE
The following equation governs how the synthesizer should be
programmed:
RF
OUT
= [INT + (FRAC/MOD)] × [F
PFD
] (3)
where:
RF
OUT
is the RF frequency output.
INT is the integer division factor.
FRAC is the fractionality.
MOD is the modulus.
The PFD frequency can be calculated as follows:
F
PFD
= REF
IN
× [(1 + D)/(R × (1 + T))] (4)
where:
REF
IN
is the reference frequency input.
D is the RF REF
IN
doubler bit.
T is the reference divide-by-2 bit, which is set to 0 or 1.
R is the RF reference division factor.
For example, in a GSM 1800 system, 1.8 GHz RF frequency
output (RF
OUT
) is required, 13 MHz reference frequency input
(REF
IN
) is available, and 200 kHz channel resolution (f
RES
) is
required on the RF output.
MOD = REF
IN
/f
RES
MOD = 13 MHz/200 kHz = 65
Therefore, from Equation 4,
F
PFD
= [13 MHz × (1 + 0)/1] = 13 MHz (5)
1.8 GHz = 13 MHz × (INT + FRAC/65) (6)
where INT = 138 and FRAC = 30.
MODULUS
The choice of modulus (MOD) depends on the reference signal
(REF
IN
) available and the channel resolution (f
RES
) required at
the RF output. For example, a GSM system with 13 MHz REF
IN
sets
the modulus to 65, resulting in the required RF output resolution
(f
RES
) of 200 kHz (13 MHz/65). With dither off, the fractional spur
interval depends on the modulus values chosen. See Table 7 for
more information.
REFERENCE DOUBLER AND REFERENCE DIVIDER
The on-chip reference doubler allows the input reference signal
to be doubled. This is useful for increasing the PFD comparison
frequency, which in turn improves the noise performance of the
system. Doubling the PFD frequency usually improves noise
performance by 3 dB. It is important to note that the PFD cannot
operate with frequencies greater than 32 MHz due to a limitation
in the speed of the Σ-Δ circuit of the N-divider.
The reference divide-by-2 divides the reference signal by 2,
resulting in a 50% duty cycle PFD frequency. This is necessary
for the correct operation of the cycle slip reduction (CSR)
function. See the Fast Lock Times section for more information.
12-BIT PROGRAMMABLE MODULUS
Unlike most other fractional-N PLLs, the ADF4156 allows the user
to program the modulus over a 12-bit range. Therefore, several
configurations of the ADF4156 are possible for an application by
varying the modulus value, the reference doubler, and the 5-bit
R-counter.
For example, consider an application that requires 1.75 GHz RF
and 200 kHz channel step resolution. The system has a 13 MHz
reference signal.
One possible setup is feeding the 13 MHz directly into the PFD
and programming the modulus to divide by 65. This results in
the required 200 kHz resolution.
Another possible setup is using the reference doubler to create
26 MHz from the 13 MHz input signal. The 26 MHz signal is then
fed into the PFD, which programs the modulus to divide by 130.
This setup also results in 200 kHz resolution, but offers superior
phase noise performance compared with the previous setup.
The programmable modulus is also useful for multistandard
applications. If a dual-mode phone requires PDC and GSM
1800 standards, the programmable modulus is a great benefit.
The PDC requires 25 kHz channel step resolution, whereas
GSM 1800 requires 200 kHz channel step resolution.
A 13 MHz reference signal can be fed directly into the PFD, and
the modulus can be programmed to 520 when in PDC mode
(13 MHz/520 = 25 kHz). However, the modulus must be
reprogrammed to 65 for GSM 1800 operation (13 MHz/65
= 200 kHz).
It is important that the PFD frequency remains constant (13 MHz).
This allows the user to design one loop filter that can be used in
both setups without running into stability issues. It is the ratio
of the RF frequency to the PFD frequency that affects the loop
design. By keeping this relationship constant, the same loop
filter can be used in both applications.
FAST LOCK TIMES WITH THE ADF4156
As mentioned in the Noise and Spur Mode section, the ADF4156
can be optimized for noise performance. However, in fast-locking
applications, the loop bandwidth needs to be wide; therefore,
the filter does not provide much attenuation of the spurs.
There are two methods of achieving a fast lock time for the
ADF4156: using cycle slip reduction or using dynamic bandwidth
switching mode. In both cases, the idea is to keep the loop band-
width narrow to attenuate spurs while obtaining a fast lock time.
Cycle slip reduction mode is the preferred technique because it
does not require modifications to the loop filter or optimization
of the timeout counter values and is therefore easier to implement.
