25
4012fa
LTC4012/
LTC4012-1/LTC4012-2
3. Place the inductor input as close as possible to the
switching FETs. Minimize the surface area of the switch
node. Make the trace width the minimum needed to
support the programmed charge current. Use no cop-
per fills or pours. Avoid running the connection on
multiple copper layers in parallel. Minimize capacitance
from the switch node to any other trace or plane.
4.
Place the charge current sense resistor immediately
adjacent to the inductor output, and orient it such
that current sense traces to the LTC4012 are not long.
These feedback traces need to be run together as a
single pair with the smallest spacing possible on any
given layer on which they are routed. Locate any filter
component on these traces next to the LTC4012, and
not at the sense resistor location.
5.
Place output capacitors adjacent to the sense resistor
output and ground.
6. Output capacitor ground connections must feed into
the same copper that connects to the input capacitor
ground before connecting back to system ground.
7. Connection
of switching ground to system ground,
or any internal ground plane, should be single-point.
If the system has an internal system ground plane,
a good way to do this is to cluster vias into a single
star point to make the connection.
8.
Route analog ground as a trace tied back to the LTC4012
GND paddle before connecting to any other ground.
Avoid using the system ground plane. A useful CAD
technique is to make analog ground a separate ground
net and use a 0Ω resistor to connect analog ground
to system ground.
9.
A
good rule of thumb for via count in a given high
current path is to use 0.5A per via. Be consistent when
applying this rule.
10. If
possible, place all the parts listed above on the same
PCB layer.
11. Copper fills or pours are good for all power connections
except as noted above in Rule 3. Copper planes on
multiple layers can also be used in parallel. This helps
with thermal management and lowers trace inductance,
which further improves EMI performance.
12.
For best current programming accuracy, provide a
Kelvin connection from R
SENSE
to CSP and CSN. See
Figure 13 for an example.
13. It
is important to minimize parasitic capacitance on
the CSP and CSN pins. The traces connecting these
pins to their respective resistors should be as short
as possible.
applications inForMation
Figure 13. Kelvin Sensing of Charge Current
TO CSP
R
IN
4012 F13
DIRECTION OF CHARGING CURRENT
R
SENSE
TO CSN
R
IN
