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843011CGLFT

P1-P3P4-P6P7-P9P10-P12P13-P14
ICS843011CG REVISION A MARCH 12, 2014 7 ©2014 Integrated Device Technology, Inc.
ICS843011C Data Sheet FEMTOCLOCK
®
CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
APPLICATION SCHEMATIC
Figure 3A
shows a schematic example of the ICS843011C. An
example of LVEPCL termination is shown in this schematic.
Additional LVPECL termination approaches are shown in the
LVPECL Termination Application Note. In this example, an 18 pF
parallel resonant 26.5625MHz crystal is used for generating
106.25MHz output frequency. The C1 = 27pF and C2 = 27pF are
recommended for frequency accuracy. For different board layout,
the C1 and C2 values may be slightly adjusted for optimizing
frequency accuracy.
FIGURE 3A. ICS843011C SCHEMATIC EXAMPLE
FIGURE 3B. ICS843011C PC BOARD LAYOUT EXAMPLE
PC BOARD LAYOUT EXAMPLE
Figure 3B
shows an example of ICS843011C P.C. board
layout. The crystal X1 footprint shown in this example allows
installation of either surface mount HC49S or through-hole HC49
package. The footprints of other components in this example are
listed in the
Table 6.
There should be at least one decoupling
capacitor per power pin. The decoupling capacitors should be
located as close as possible to the power pins. The layout assumes
that the board has clean analog power ground plane.
TABLE 6. FOOTPRINT TABLE
ecnerefeReziS
2C,1C2040
3C5080
5C,4C3060
2R3060
tnenopmocstsil,6elbaT:ETON
.elpmaxetuoyalsihtninwohssezis
R5
50
Zo = 50 Ohm
C4
0.1u
C2
33pF
XTAL_IN
Q
nQ
VCCA
R5
133
R2
10
Zo = 50 Ohm
C5
0.1u
R6
50
Zo = 50 Ohm
R4
82.5
+
-
Optional
Y-Termination
Q
XTAL_OUT
X1
26.5625MHz
Zo = 50 Ohm
nQ
VCC
VCC
C1
27pF
+
-
R7
50
U2
843011C
1
2
3
4
8
7
6
5
VCCA
VEE
XTA L_ OU T
XTA L_ I N
VCC
Q
nQ
nc
R6
82.5
C3
10uF
VCC
R3
133
843011C
27pF
ICS843011CG REVISION A MARCH 12, 2014 8 ©2014 Integrated Device Technology, Inc.
ICS843011C Data Sheet FEMTOCLOCK
®
CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843011C.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843011C is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 90mA = 311.85mW
• Power (outputs)
MAX
= 30mW/Loaded Output pair
Total Power
_MAX
(3.465V, with all outputs switching) = 311.85mW + 30mW = 341.85mW
2. Junction Temperature.
Junction temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum
recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the
bond wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θ
JA
* Pd_total + T
A
Tj = Junction Temperature
θ
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
JA
must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 5 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.342W * 90.5°C/W = 101°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and
the type of board (single layer or multi-layer).
TABLE 5. THERMAL RESISTANCE
θθ
θθ
θ
JA
FOR 8-PIN TSSOP, FORCED CONVECTION
θθ
θθ
θ
JA
by Velocity (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W
ICS843011CG REVISION A MARCH 12, 2014 9 ©2014 Integrated Device Technology, Inc.
ICS843011C Data Sheet FEMTOCLOCK
®
CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 4.
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V
CC
- 2V.
• For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
– 0.9V
(V
CCO_MAX
- V
OH_MAX
)
= 0.9V
• For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
– 1.7V
(V
CCO_MAX
- V
OL_MAX
)
= 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OH_MAX
) = [(2V - (V
CC
_MAX
- V
OH_MAX
))
/R
L
] * (V
CC_MAX
- V
OH_MAX
) =
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
– (V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OL_MAX
) = [(2V - (V
CC
_MAX
- V
OL_MAX
))
/R
L
] * (V
CC_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION
Q1
V
OUT
V
CC
RL
50
V
CC
- 2V
P1-P3P4-P6P7-P9P10-P12P13-P14

843011CGLFT

Mfr. #:
Buy 843011CGLFT
Manufacturer:
IDT
Description:
Clock Generators & Support Products 1 LVPECL OUT SYNTHESIZER
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