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A1244LUA-I1-T

P1-P3P4-P6P7-P9P10-P12
Chopper-Stabilized, Two-Wire
Hall-Effect Latch
A1244
7
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Functional Description
B
OP
B
RP
B
HYS
I
CC(H)
I
CC
I
CC(L)
Switch to High
Switch to Low
B+
I+
B–
0
The A1244 output, I
CC
, switches high after the magnetic field
at the Hall sensor IC exceeds the operate point threshold, B
OP
.
When the magnetic field is reduced to below the release point
threshold, B
RP
, the device output goes low. This is shown in
figure 1.
The difference between the magnetic operate and release points
is called the hysteresis of the device, B
HYS
. This built-in hyster-
esis allows clean switching of the output even in the presence of
external mechanical vibration and electrical noise.
Figure 1. Hysteresis for the A1244. On the horizontal axis, the B+ direc-
tion indicates increasing south polarity magnetic field strength, and the
B– direction indicates decreasing south polarity field strength (including
the case of increasing north polarity).
Chopper-Stabilized, Two-Wire
Hall-Effect Latch
A1244
8
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Figure 2. Typical application circuits
GND
A1244
VCC
V+
0.01 µF
ECU
R
SENSE
C
BYP
GND
A1244
VCC
V+
0.01 µF
R
SENSE
C
BYP
(A) Low side sensing (B) High side sensing
Amp
Regulator
Clock/Logic
Hall Element
Sample and
Hold
Low-Pass
Filter
Chopper Stabilization Technique
When using Hall-effect technology, a limiting factor for
switchpoint accuracy is the small signal voltage developed
across the Hall element. This voltage is disproportionally small
relative to the offset that can be produced at the output of the
Hall sensor IC. This makes it difficult to process the signal while
maintaining an accurate, reliable output over the specified oper-
ating temperature and voltage ranges. Chopper stabilization is
a unique approach used to minimize Hall offset on the chip. The
Allegrotechnique,namelyDynamicQuadratureOffsetCancella-
tion, removes key sources of the output drift induced by thermal
and mechanical stresses. This offset reduction technique is based
on a signal modulation-demodulation process. The undesired
offset signal is separated from the magnetic field-induced signal
in the frequency domain, through modulation. The subsequent
demodulation acts as a modulation process for the offset, causing
the magnetic field-induced signal to recover its original spectrum
atbaseband,whiletheDCoffsetbecomesahigh-frequencysig-
nal. The magnetic-sourced signal then can pass through a low-
passfilter,whilethemodulatedDCoffsetissuppressed.The
chopper stabilization technique uses a 350 kHz high frequency
clock. For demodulation process, a sample and hold technique is
used, where the sampling is performed at twice the chopper fre-
quency. This high-frequency operation allows a greater sampling
rate, which results in higher accuracy and faster signal-process-
ing capability. This approach desensitizes the chip to the effects
of thermal and mechanical stresses, and produces devices that
have extremely stable quiescent Hall output voltages and precise
recoverability after temperature cycling. This technique is made
possible through the use of a BiCMOS process, which allows
the use of low-offset, low-noise amplifiers in combination with
high-density logic integration and sample-and-hold circuits.
Figure 3. Chopper stabilization circuit (Dynamic Quadrature Offset Cancellation)
Chopper-Stabilized, Two-Wire
Hall-Effect Latch
A1244
9
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
The device must be operated below the maximum junction tem-
perature of the device, T
J
(max). Under certain combinations of
peak conditions, reliable operation may require derating supplied
power or improving the heat dissipation properties of the appli-
cation. This section presents a procedure for correlating factors
affecting operating T
J
. (Thermal data is also available on the
Allegro MicroSystems Web site.)
ThePackageThermalResistance,R
θJA
, is a figure of merit sum-
marizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
ItsprimarycomponentistheEffectiveThermalConductivity,K,
of the printed circuit board, including adjacent devices and traces.
Radiationfromthediethroughthedevicecase,R
θJC
, is relatively
smallcomponentofR
θJA
. Ambient air temperature, T
A
, and air
motion are significant external factors, damped by overmolding.
Theeffectofvaryingpowerlevels(PowerDissipation,P
D
), can
be estimated. The following formulas represent the fundamental
relationships used to estimate T
J
, at P
D
.
P
D
=V
IN
×
I
IN
(1)
ΔT = P
D
×
R
θJA
(2)
T
J
= T
A
+ΔT (3)
For example, given common conditions such as: T
A
= 25°C,
V
CC
= 12V, I
CC
= 4 mA, and R
θJA
= 140 °C/W, then:
P
D
=V
CC
×
I
CC
=12V
×
4 mA = 48 mW
ΔT = P
D
×
R
θJA
= 48 mW
×
140°C/W=7°C
T
J
= T
A
+ ΔT=25°C+7°C=32°C
A worst-case estimate, P
D
(max), represents the maximum allow-
ablepowerlevel(V
CC
(max), I
CC
(max)), without exceeding
T
J
(max),ataselectedR
θJA
and T
A
.
Example:ReliabilityforV
CC
at T
A
=
150°C, package LH, using a
low-KPCB.
Observe the worst-case ratings for the device, specifically:
R
θJA
=
110 °C/W, T
J
(max)
=
165°C,V
CC
(max)
=
24V,and
I
CC
(max)
=
17
mA.
Calculate the maximum allowable power level, P
D
(max). First,
invert equation 3:
ΔT
max
= T
J
(max) – T
A
=165
°C
–
150
°C = 15
°C
This provides the allowable increase to T
J
resulting from internal
power dissipation. Then, invert equation 2:
P
D
(max)
= ΔT
max
÷ R
θJA
=15°C÷110°C/W=136mW
Finally, invert equation 1 with respect to voltage:
 V
CC(est)
= P
D
(max)
÷ I
CC
(max) =136mW÷17mA = 8V
The result indicates that, at T
A
, the application and device can
dissipateadequateamountsofheatatvoltages≤V
CC(est)
.
CompareV
CC(est)
toV
CC
(max).IfV
CC(est)
≤V
CC
(max), then reli-
ableoperationbetweenV
CC(est)
andV
CC
(max) requires enhanced
R
θJA
.IfV
CC(est)
≥V
CC
(max),thenoperationbetweenV
CC(est)
andV
CC
(max) is reliable under these conditions.
Power Derating
P1-P3P4-P6P7-P9P10-P12

A1244LUA-I1-T

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MAGNETIC SWITCH LATCH 3SIP
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