2
DS 138 Rev I | 04/07/06
S1700/S1750 Series
5V CMOS/TTL, SMD
Crystal Clock Oscillator (XO)
Pericom Semiconductor Corporation • 1-800-435-2336 • http://www.pericom.com/saronix
All specifications are subject to change without notice.
Not for new designs - see S1615 series
Electrical Performance
Parameter Min. Typ. Max. Units Notes
Output frequency 1.8432 80 MHz S1750 Max Frequency 67 MHz
Supply voltage +4.5 +5.0 +5.5 V DC
Supply current, output enabled
1700
15
mA
1.8 to 35 MHz
30 >35 to 66.0 MHz
50 >66 to 80.0 MHz
Supply current, output enabled
1750
20
mA
1.8 to 20 MHz
35 >20 to 50 MHz
60 >50 to 67.0 MHz
Frequency stability
±50 to
±100
ppM See Note 1 below
Operating temperature 0 +70 °C
Output logic 0, VOL
10% V
DD
V HCMOS
0.5 V TTL, S1750 only
Output logic 1, VOH
90% V
DD
V HCMOS
2.5 V TTL, S1750 only
Output load
15 pF S1700
50 pF S1750
5 TTL TTL, S1750 only
Duty cycle
CMOS 45 55 % 0 to 70°C measured 50%VDD
TTL 40 60 % 0 to 70°C measured 1.5V, S1750 only
Rise and fall
time
CMOS 10 ns measured 20/80% of waveform
TTL 5 ns measured 0.5V to 2.5V, S1750 only
Note:
1. As specied. Stability includes all combinations of operating temperature, load changes, rated input (supply) voltage changes, initial calibration tolerance (25°C),
aging (1 year at 25°C average effective ambient temperature), shock and vibration.
Output Enable / Disable Function
Parameter Min. Typ. Max. Units Notes
Input Voltage (pin 1), Output
Enable (HCMOS)
90% V
DD
V or open
Input voltage (pin 1), Output
Disable (HCMOS)
10% V
DD
V Output is Hi-Z
Input voltage (pin 1), Output
Enable (TTL)
2.2 V or open
Input voltage (pin 1), Output
Disable (TTL)
0.8 V Output is Hi-Z
Internal pullup resistance 50 kΩ
Output disable delay 100 ns
Output enable delay 100 ns
