7
Write Cycle Timing Diagram
AC Timing Characteristics Over Temperature Range (-45°C to +85°C)
4.5 V < V
DD
< 5.5 V, unless otherwise specied
Symbol Description 25°C Typ. Min.
[1]
Units
F
OSC
Oscillator Frequency 57 28 kHz
F
RF
[2]
Display Refresh Rate 256 128 Hz
F
FL
[3]
Character Flash Rate 2 1 Hz
t
ST
[4]
Self Test Cycle Time 4.6 9.2 sec
Notes:
1. Worst case values occur at an IC junction temperature of 150°C.
2. F
RF
= F
OSC
/224.
3. F
FL
= F
OSC
/28,672.
4. t
ST
= 262,144/F
OSC
.
1
9
8
6
32
CE
7
10
4 2
5
A
0
-A
4
FL
D
0
-D
7
WR
INPUT PULSE LEVELS: 0.6 V to 2.4 V
8
Read Cycle Timing Diagram
Relative Luminous Intensity vs. Temperature
1
12
11
6
3
2
CE
7
13
4 2
5
A
0
-A
4
FL
D
0
-D
7
RD
INPUT PULSE LEVELS: 0.6 V to 2.4 V
OUTPUT REFERENCE LEVELS: 0.6 V to 2.2 V
OUTPUT LOADING = 1 TTL LOAD AND 100 pF
RELATIVE LUMINOUS INTENSITY
(NORMALIZED TO 1 AT 25°C)
-55
0
T
A
– AMBIENT TEMPERATURE – °C
65
-35
45 85
3.5
3.0
2.5
1.5
1.0
0.5
525-15
2.0
-45
HER HDSP-2112/2502
ORANGE HDSP-2110/2500
YELLOW HDSP-2111/2501
GREEN
HDSP-2113/2503
9
Electrical Description
Pin Function Description
RESET (RST, pin 1) Initializes the display.
FLASH (FL, pin 2) FL low indicates an access to the Flash RAM and is unaffected by the
state of address lines A
3
-A
4
.
ADDRESS INPUTS Each location in memory has a distinct address. Address inputs (A
0
-A
2
)
(A
0
-A
4
, pins 3-6, 10) select a specific location in the Character RAM, the Flash RAM or a
particular row in the UDC (User-Defined Character) RAM. A
3
-A
4
are used
to select which section of memory is accessed. Table 1 shows the
logic levels needed to access each section of memory.
Table 1. Logic Levels to Access Memory
Section of Memory FL A
4
A
3
A
2
A
1
A
0
Flash RAM 0 X X Char. Address
UDC Address Register 1 0 0 Don’t Care
UDC RAM 1 0 1 Row Address
Control Word Register 1 1 0 Don’t Care
Character RAM 1 1 1 Character Address
CLOCK SELECT Used to select either an internal (CLS = 1) or external (CLS = 0) clock source.
(CLS, pin 11)
CLOCK INPUT/OUTPUT Outputs the master clock (CLS = 1) or inputs a clock (CLS = 0) for slave displays.
(CLK, pin 12)
WRITE (WR, pin 13) Data is written into the display when the WR input is low and the CE input is low.
CHIP ENABLE (CE, pin 17) Must be at a logic low to read or write data to the display and must go high between
each read and write cycle.
READ (RD, pin 18) Data is read from the display when the RD input is low and the CE input is low.
DATA Bus (D
0
-D
7
, Used to read from or write to the display.
pins 19, 20, 23-28)
GND (SUPPLY) (pin 15) Analog ground for the LED drivers.
GND (LOGIC) (pin 16) Digital ground for internal logic.
V
DD
(POWER) (pin 14) Positive power supply input.

HDSP-2112-IJ000

Mfr. #:
Manufacturer:
Broadcom / Avago
Description:
LED Displays & Accessories Red 626nm 5x7 Smart Display
Lifecycle:
New from this manufacturer.
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