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LTC4446IMS8E#PBF

P1-P3P4-P6P7-P9P10-P12
LTC4446
7
4446f
OPERATION
Overview
The LTC4446 receives ground-referenced, low voltage digi-
tal input signals to drive two N-channel power MOSFETs in
a synchronous buck power supply confi guration. The gate
of the low side MOSFET is driven either to V
CC
or GND,
depending on the state of the input. Similarly, the gate of
the high side MOSFET is driven to either BOOST or TS by
a supply bootstrapped off of the switching node (TS).
Input Stage
The LTC4446 employs CMOS compatible input thresholds
that allow a low voltage digital signal to drive standard
power MOSFETs. The LTC4446 contains an internal
voltage regulator that biases both input buffers for high
side and low side inputs, allowing the input thresholds
(V
IH
= 2.75V, V
IL
= 2.3V) to be independent of variations in
V
CC
. The 450mV hysteresis between V
IH
and V
IL
eliminates
false triggering due to noise during switching transitions.
However, care should be taken to keep both input pins
(TINP and BINP) from any noise pickup, especially in high
frequency, high voltage applications. The LTC4446 input
buffers have high input impedance and draw negligible
input current, simplifying the drive circuitry required for
the inputs.
Output Stage
A simplifi ed version of the LTC4446’s output stage is shown
in Figure 1. The pull-up devices on the BG and TG outputs
are NPN bipolar junction transistors (Q1 and Q2). The BG
and TG outputs are pulled up to within an NPN V
BE
(~0.7V)
of their positive rails (V
CC
and BOOST, respectively). Both
BG and TG have N-channel MOSFET pull-down devices
(M1 and M2) which pull BG and TG down to their nega-
tive rails, GND and TS. The large voltage swing of the BG
and TG output pins is important in driving external power
MOSFETs, whose R
DS(ON)
is inversely proportional to the
gate overdrive voltage (V
GS
− V
TH
).
Rise/Fall Time
The LTC4446’s rise and fall times are determined by the
peak current capabilities of Q1 and M1. The predriver that
drives Q1 and M1 uses a nonoverlapping transition scheme
to minimize cross-conduction currents. M1 is fully turned
off before Q1 is turned on and vice versa.
Since the power MOSFET generally accounts for the ma-
jority of the power loss in a converter, it is important to
quickly turn it on or off, thereby minimizing the transition
time in its linear region. An additional benefi t of a strong
pull-down on the driver outputs is the prevention of cross-
conduction current. For example, when BG turns the low
side (synchronous) power MOSFET off and TG turns the
high side power MOSFET on, the voltage on the TS pin
will rise to V
IN
very rapidly. This high frequency positive
voltage transient will couple through the C
GD
capacitance
of the low side power MOSFET to the BG pin. If there is
an insuffi cient pull-down on the BG pin, the voltage on
the BG pin can rise above the threshold voltage of the low
side power MOSFET, momentarily turning it back on. With
Figure 1. Capacitance Seen by BG and TG During Switching
6
BOOST
LTC4446
8
TS
TG
7
V
IN
UP TO 100V
Q1
M1
C
GS
4446 F01
C
GD
3
V
CC
9
GND
4
BG
Q2
M2
LOW SIDE
POWER
MOSFET
HIGH SIDE
POWER
MOSFET
C
GS
C
GD
LOAD
INDUCTOR
LTC4446
8
4446f
OPERATION
both the high side and low side MOSFETs conducting,
signifi cant cross-conduction current will fl ow through the
MOSFETs from V
IN
to ground and will cause substantial
power loss. A similar effect occurs on TG due to the C
GS
and C
GD
capacitances of the high side MOSFET.
The powerful output driver of the LTC4446 reduces the
switching losses of the power MOSFET, which increase
with transition time. The LTC4446’s high side driver is
capable of driving a 1nF load with 8ns rise and 5ns fall
times using a bootstrapped supply voltage V
BOOST-TS
of
12V while its low side driver is capable of driving a 1nF
Power Dissipation
To ensure proper operation and long-term reliability, the
LTC4446 must not operate beyond its maximum tem-
perature rating. Package junction temperature can be
calculated by:
T
J
= T
A
+ P
D
(θ
JA
)
where:
T
J
= Junction temperature
T
A
= Ambient temperature
P
D
= Power dissipation
θ
JA
= Junction-to-ambient thermal resistance
Power dissipation consists of standby and switching
power losses:
P
D
= P
DC
+ P
AC
+ P
QG
where:
P
DC
= Quiescent power loss
P
AC
= Internal switching loss at input frequency, f
IN
P
QG
= Loss due turning on and off the external MOSFET
with gate charge QG at frequency f
IN
load with 6ns rise and 3ns fall times using a supply volt-
age V
CC
of 12V.
Undervoltage Lockout (UVLO)
The LTC4446 contains an undervoltage lockout detector
that monitors V
CC
supply. When V
CC
falls below 6.15V,
the output pins BG and TG are pulled down to GND and
TS, respectively. This turns off both external MOSFETs.
When V
CC
has adequate supply voltage, normal operation
will resume.
APPLICATIONS INFORMATION
The LTC4446 consumes very little quiescent current. The
DC power loss at V
CC
= 12V and V
BOOST-TS
= 12V is only
(350μA)(12V) = 4.2mW.
At a particular switching frequency, the internal power loss
increases due to both AC currents required to charge and
discharge internal node capacitances and cross-conduc-
tion currents in the internal logic gates. The sum of the
quiescent current and internal switching current with no
load are shown in the Typical Performance Characteristics
plot of Switching Supply Current vs Input Frequency.
The gate charge losses are primarily due to the large AC
currents required to charge and discharge the capacitance
of the external MOSFETs during switching. For identical
pure capacitive loads C
LOAD
on TG and BG at switching
frequency f
IN
, the load losses would be:
P
CLOAD
= (C
LOAD
)(f)[(V
BOOST-TS
)
2
+ (V
CC
)
2
]
In a typical synchronous buck confi guration, V
BOOST-TS
is equal to V
CC
– V
D
, where V
D
is the forward voltage
drop across the diode between V
CC
and BOOST. If this
drop is small relative to V
CC
, the load losses can be
approximated as:
P
CLOAD
= 2(C
LOAD
)(f
IN
)(V
CC
)
2
LTC4446
9
4446f
APPLICATIONS INFORMATION
Unlike a pure capacitive load, a power MOSFET’s gate
capacitance seen by the driver output varies with its V
GS
voltage level during switching. A MOSFET’s capacitive load
power dissipation can be calculated using its gate charge,
Q
G
. The Q
G
value corresponding to the MOSFET’s V
GS
value (V
CC
in this case) can be readily obtained from the
manufacturer’s Q
G
vs V
GS
curves. For identical MOSFETs
on TG and BG:
P
QG
= 2(V
CC
)(Q
G
)(f
IN
)
To avoid damage due to power dissipation, the LTC4446
includes a temperature monitor that will pull BG and TG
low if the junction temperature rises above 160°C. Normal
operation will resume when the junction temperature cools
to less than 135°C.
Bypassing and Grounding
The LTC4446 requires proper bypassing on the V
CC
and V
BOOST-TS
supplies due to its high speed switching
(nanoseconds) and large AC currents (Amperes). Careless
component placement and PCB trace routing may cause
excessive ringing.
To obtain the optimum performance from the LTC4446:
A. Mount the bypass capacitors as close as possible
between the V
CC
and GND pins and the BOOST and
TS pins. The leads should be shortened as much as
possible to reduce lead inductance.
B. Use a low inductance, low impedance ground plane
to reduce any ground drop and stray capacitance.
Remember that the LTC4446 switches greater than
3A peak currents and any signifi cant ground drop will
degrade signal integrity.
C. Plan the power/ground routing carefully. Know where
the large load switching current is coming from and
going to. Maintain separate ground return paths for
the input pin and the output power stage.
D. Keep the copper trace between the driver output pin
and the load short and wide.
E. Be sure to solder the Exposed Pad on the back side of
the LTC4446 package to the board. Correctly soldered
to a 2500mm
2
doublesided 1oz copper board, the
LTC4446 has a thermal resistance of approximately
40°C/W for the MS8E package. Failure to make good
thermal contact between the exposed back side and
the copper board will result in thermal resistances far
greater than 40°C/W.
P1-P3P4-P6P7-P9P10-P12

LTC4446IMS8E#PBF

Mfr. #:
Buy LTC4446IMS8E#PBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Gate Drivers Hi V Hi Side / L Side N-Ch MOSFET Drvr
Lifecycle:
New from this manufacturer.
Delivery:
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