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EL5000AERZ-T13

P1-P3P4-P6P7-P9P10-P12
10
FN6167.2
February 20, 2008
Output Waveforms
Figure 21 shows a typical CKV and CKVB output
waveforms. The output droop rate depends on the external
discharge resistor value and the output capacitor load.
Figure 22 shows the delay time between the incoming
horizontal sync timing pulse CPV and the generated output
pulses. Δt is dependent mainly on the value of C
L
. Figure 23
shows the effect of STV.
Auxiliary Functions
DISH: It discharges V
OFF
when the logic power voltage level
drops out, when 'DISH' is < -0.6V (V
CC
system power turns
off), V
OFF
is connected to ground level by 1kΩ.
OECON: It provides continuos polarity changes to the
TFT-LCD panel during the vertical blanking.
FIGURE 21. CKV AND CKVB OUTPUT WAVEFORMS
FIGURE 22. CPV TO CKV/CKVB DELAY
CKV
CKVB
CKV
CKVB
CPV
FIGURE 23. EFFECT OF STV
CKV
CKVB
STV
CPV
FIGURE 24. TYPICAL APPLICATION CIRCUIT
VCC
C4
1µF
C1
0.1µF
C2
0.1µF
+18V TO +40V
VSYNC TIMING
HSYNC TIMING
WRITING TIMING
TFT-LCD
C3
22µF
C10
2nF*
ca 20k*
R6
C8
0.1µF
C9
22µF
-9V TO -20V
EL5000
R2 5k
R3
5k
DISCH
OECON
STV
CPV
OE
CKV
CKVCS
CKVB
CKVBCS
STVP
VDD
VON
GND
GND
VOFF
15
14
12
10
11
2
3
6
5
7
R
R
R
C
C
C
16
1
9
13
8
EL5000A
11
FN6167.2
February 20, 2008
Power Dissipation
The dissipated power in R
3
and R
6
could be calculated as
follows:
We assume that:
•V
ON
= 40V
•V
OFF
= -20V
• H sync timing frequency = 60kHz
•C
L
= 5nF
The value of V
L
(the left over voltage) in the capacitors in
that case is 23V for the positive discharge and 3.3V for the
negative discharge.
The voltage change across the capacitor is therefore 23V;
see Figure 25.
The stored energy in the capacitor is shown in Equation 1:
The energy, which is stored in the capacitor, will be
dissipated on the resistor; see Figure 26. The switch will
close 2 x 60,000 in every second.
The process will be repeated 2 times for the CKV and the
CKVB. In 120,000 cycles per second, the power dissipation
in R
3
and R
6
becomes Equation 2:
For different values of V
ON
, V
OFF
, C
L
and H sync timing
frequency, the worst case dissipation can be calculated in a
similar matter. The value of the R
3
and R
6
must be selected
such that the capacitor C
L
is discharged via R
3
or R
6
resistor
in one half period of the H sync timing.
Figures 13 and 14 show the total power dissipation over a
range of possible voltages, operating frequencies and loads.
Care should be taken to prevent the power from exceeding
the maximum rating of the package, as shown in Figure 13.
1/2 V×
2
C1/223
2
5× 10
-9
×× 132μJ==
(EQ. 1)
21.3210
-6
60 10×
3
××× 160mW=
(EQ. 2)
+17 V
+40V
23V
0 V
+3.3
V
-20V
23V
FIGURE 25.
FIGURE 26.
EL5000A
12
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6167.2
February 20, 2008
EL5000A
Thin Shrink Small Outline Package Family (TSSOP)
N
(N/2)+1
(N/2)
TOP VIEW
AD
0.20 C
2X
B A
N/2 LEAD TIPS
B
E1
E
0.25 CAB
M
1
H
PIN #1 I.D.
0.05
e
C
0.10 C
N LEADS
SIDE VIEW
0.10 CABM
b
c
SEE DETAIL “X”
END VIEW
DETAIL X
A2
0° - 8°
GAUGE
PLANE
0.25
L
A1
A
L1
SEATING
PLANE
MDP0044
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY
SYMBOL
MILLIMETERS
TOLERANCE14 LD 16 LD 20 LD 24 LD 28 LD
A 1.20 1.20 1.20 1.20 1.20 Max
A1 0.10 0.10 0.10 0.10 0.10 ±0.05
A2 0.90 0.90 0.90 0.90 0.90 ±0.05
b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06
c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06
D 5.00 5.00 6.50 7.80 9.70 ±0.10
E 6.40 6.40 6.40 6.40 6.40 Basic
E1 4.40 4.40 4.40 4.40 4.40 ±0.10
e 0.65 0.65 0.65 0.65 0.65 Basic
L 0.60 0.60 0.60 0.60 0.60 ±0.15
L1 1.00 1.00 1.00 1.00 1.00 Reference
Rev. F 2/07
NOTES:
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
3. Dimensions “D” and “E1” are measured at dAtum Plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
P1-P3P4-P6P7-P9P10-P12

EL5000AERZ-T13

Mfr. #:
Buy EL5000AERZ-T13
Manufacturer:
Renesas / Intersil
Description:
IC DRIVER TFT-LCD HV 16TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
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