1–6 Chapter 1: Stratix III Device Family Overview
Architecture Features
Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation
Architecture Features
The following section describes the various features of the Stratix III family FPGAs.
Logic Array Blocks and Adaptive Logic Modules
The Logic Array Block (LAB) is composed of basic building blocks known as
Adaptive Logic Modules (ALMs) that can be configured to implement logic,
arithmetic, and register functions. Each LAB consists of ten ALMs, carry chains,
shared arithmetic chains, LAB control signals, local interconnect, and register chain
connection lines. ALMs are part of a unique, innovative logic structure that delivers
faster performance, minimizes area, and reduces power consumption. ALMs expand
the traditional 4-input look-up table architecture to 7 inputs, increasing performance
by reducing LEs, logic levels, and associated routing. In addition, ALMs maximize
DSP performance with dedicated functionality to efficiently implement adder trees
and other complex arithmetic functions. The Quartus II Compiler places associated
logic in an LAB or adjacent LABs, allowing the use of local, shared arithmetic chain,
and register chain connections for performance and area efficiency.
The Stratix III LAB has a new derivative called Memory LAB (or MLAB), which adds
SRAM memory capability to the LAB. MLAB is a superset of the LAB and includes all
LAB features. MLABs support a maximum of 320 bits of simple dual-port Static
Random Access Memory (SRAM). Each ALM in an MLAB can be configured as a
16×2 block, resulting in a configuration of 16×20 simple dual port SRAM block. MLAB
and LAB blocks always co-exist as pairs in all Stratix III families, allowing up to 50%
of the logic (LABs) to be traded for memory (MLABs).
f For more information about LABs and ALMs, refer to the Logic Array Blocks and
Adaptive Logic Modules in Stratix III Devices chapter.
f For more information about MLAB modes, features and design considerations, refer
to the TriMatrix Embedded Memory Blocks in Stratix III Devices chapter.
EP3SE260
Commercial — —
–2, –3, –4,
–4L
–2,– 3, –4,
–4L
—
–2, –3, –4,
–4L
—
Industrial (1) — — –3, –4, –4L –3, –4, –4L — –3, –4,–4L —
Note to Table 1–5:
(1) For EP3SL340, EP3SL200, and EP3SE260 devices, the industrial junction temperature range for –4L is 0–100°C, regardless of supply voltage.
Table 1–5. Speed Grades for Stratix III Devices (Part 2 of 2)
Device
Temperature
Grade
484 -Pin
FineLine
BGA
780-Pin
FineLine
BGA
780-Pin
Hybrid
FineLine
BGA
1152-Pin
FineLine
BGA
1152-Pin
Hybrid
FineLine
BGA
1517-Pin
FineLine
BGA
1760-Pin
FineLine
BGA
