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XRT5683AIP-F

P1-P3P4-P6P7-P9P10-P12
XR-T5683A
...the analog plus company
TM
PCM Line
Interface Chip
Rev. 2.0.2
2010
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 (510) 668-7000 FAX (510) 668-7017
1
October 2010
FEATURES
Single 5V Supply
Receiver Input Can Be Either Balanced or
Unbalanced
Up To 8.448Mbps Operation In Both Tx and Rx
Directions
TTL Compatible Interface
Device Can Be Used as a Line Interface Unit With-
out Clock Recovery
APPLICATIONS
T1, T2, E1 & E2 Rates, PCM Line Interface
Network Multiplexing and Terminating Equipment
GENERAL DESCRIPTION
The XR-T5683A is a PCM line interface chip consisting of
both transmit and receive circuitry. This device is offered
in a plastic dual in-line (PDIP) or in a surface mount
package (SOIC). The maximum bit rate of the chip is
8.448Mbps, and the signal level to the receiver can be
attenuated by -10dB cable loss at one-half the bit rate. At
nominal supply voltage operation, the typical current
consumption is 40mA.
ORDERING INFORMATION
Part No. Package
Operating
Temperature Range
XR-T5683AIP 18 Lead 300 Mil PDIP -40°C to +85°C
XR-T5683AID 18 Lead 300 Mil JEDEC SOIC -40°C to +85°C
BLOCK DIAGRAM
Figure 1. Block Diagram
RPOS
11
Positive
Threshold
Comparator
PDC
1
Peak
Detector
BIAS
RXDATA-
2
RXDATA+ 3
Negative
Threshold
Comparator
TE
4
TTLBuffer
TANK BIAS
6
RNEG
10
RCLK
8
BIAS
5
TXDATA+
13
Open Collector
Driver
BIAS
TV
CC
18
RGND
7
RV
CC
9
TPOS 17
TCLK
16
TNEG
12
TGND
14
TXDATA-
15
Open Collector
Driver
TTLBuffer
TTLBuffer
XR-T5683A
2
Rev. 2.0.2
PIN CONFIGURATION
18 Lead PDIP (0.300”)
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
TV
CC
TPOS
TCLK
TXDATA-
PDC
RXDATA-
RXDATA+
TE
TGND
TXDATA+
TNEG
RPOS
BIAS
TANK BIAS
RGND
RCLK
RNEGRV
CC
18 Lead SOIC (JEDEC, 0.300”)
181
109
2
3
4
5
6
7
15
14
13
12
11
17
16
8
PDC
RXDATA-
RXDATA+
TE
BIAS
TANK BIAS
RGND
RCLK
RV
CC
TV
CC
TPOS
TCLK
TXDATA-
TGND
TXDATA+
TNEG
RPOS
RNEG
PIN DESCRIPTION
Pin # Symbol Type Description
1 PDC Peak Detector Capacitor. This pin should be connected to a 0.1µF capacitor.
2 RXDATA- I Receive Analog Input Positive. Line analog input.
3 RXDATA+ I Receive Analog Input Negative. Line analog input.
4 TE O Tank Excitation Output. This output connects to one side of the tank circuitry.
5 BIAS O Bias. This output is to be connected to the center tap of the receive transformer.
6 TANK BIAS O Tank Bias. The tank circuitry is biased via this output.
7 RGND Receiver Ground. To minimize ground interference a separate pin is used to ground the
receive section.
8 RCLK O Recovered Receive Clock. Recovered clock signal to the terminal equipment.
9 RV
CC
Receive Supply Voltage. 5V supply voltage to the receive section.
10 RNEG O Receive Negative Data. Negative pulse data output to the terminal equipment (active low).
11 RPOS O Receive Positive Data. Positive pulse data output to the terminal equipment (active low).
12 TNEG I Transmit Negative Data. TNEG is valid while TCLK is high.
13 TXDATA+ O Transmit Positive Output. Transmit bipolar signal is driven to the line via a transformer.
14 TGND Transmit Ground.
15 TXDATA- O Transmit Negative Output. Transmit bipolar signal is driven to the line via a transformer.
16 TCLK I Transmit Clock. Timing element for TPOS and TNEG.
17 TPOS I Transmit Positive Data. TPOS is valid while TCLK is high.
18 TV
CC
Transmit Supply Voltage. 5V supply voltage to the transmit section.
XR-T5683A
3
Rev. 2.0.2
ELECTRICAL CHARACTERISTICS
Test Conditions: V
CC
= 5.0V 5%, T
A
= 25°C, Unless Otherwise Specified.
Parameters Min. Typ. Max. Unit Conditions
DC Electrical Characteristics
Supply Voltage 4.75 5 5.25 V
Supply Current 40 55 mA Total Current to Pin 9 & Pin 18
Transmitter Outputs Open
Receiver Section
Tank Drive Current 300 500 700 µA Measured at Pin 4, V
CC
= 5V
Clock Output Low 0.3 0.6 V Measured at Pin 8, I
OL
= 1.6mA
Clock Output High 3.0 3.6 V Measured at Pin 8, I
OH
= -400µA
Data Output Low 0.3 0.6 V Measured at Pin 10 & 11, I
OL
= 1.6mA
Data Output High 3.0 3.6 V Measured at Pin 10 & 11, I
OH
= -400µA
Transmitter Section
Driver Output Low 0.6 0.8 1.0 V Measured at Pin 13 & 15, I
OL
= 40mA
Output Leakage Current 0 100 µA Measured in Off State, Output Pull-up to
+ 20V
Input High Voltage 2.2 V
CC
V Measured at Pin 12, 16 & 17, I
OL
= 40mA,
V
OL
= 1.0V
Input Low Voltage 0.8 V Measured at Pin 12, 16 & 17, Output Off
Input Low Current -1.6 mA Measured at Pin 12, 16 & 17, Input Low
Voltage = 0. 4V
Input High Current 40 µA Measured at Pin 12, 16 & 17, Input High
Voltage = 2.7V
Output Low Current 40 mA Measured at Pin 13 & 15, V
OL
= 1.0V
AC Electrical Characteristics
Receiver Section
Input Level 6 6.6 Vpp Measured Between Pin 2 & 3
Loss Input Signal Alarm Level 1.6 Vpp Measured Between Pin 2 & 3, Alarm on
Pull Data Output High
Input Impedance at 8,448MHz 2.5 kΩ Measured Between Pin 2 & 3, With
Sinewave Input
Clock Duty Cycle 35 50 65 % Measured at Pin 8 at 2.0V
Clock Rise & Fall Time 20 ns Measured at Pin 8, C
L
= 15pF
Data Pulse Width 35 50 75 % of
clock
period
Measured at Pin 10 & 11, at 1V DC
Level, Cable Loss = 0
Notes
Bold face parameters are covered by production test and guaranteed over operating temperature range.
P1-P3P4-P6P7-P9P10-P12

XRT5683AIP-F

Mfr. #:
Buy XRT5683AIP-F
Manufacturer:
MaxLinear
Description:
Telecom Interface ICs
Lifecycle:
New from this manufacturer.
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