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P87LPC760BN,112

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P56
Philips Semiconductors Preliminary data
P87LPC760
Low power, low price, low pin count (14 pin)
microcontroller with 1 kbyte OTP
2002 Mar 07
22
SU01538
87LPC760
QUARTZ CRYSTAL OR
CERAMIC RESONATOR
X2
X1
THE OSCILLATOR MUST BE CONFIGURED IN ONE OF
THE FOLLOWING MODES:
– LOW FREQUENCY CRYSTAL
– MEDIUM FREQUENCY CRYSTAL
– HIGH FREQUENCY CRYSTAL
*
CAPACITOR VALUES MAY BE OPTIMIZED FOR
DIFFERENT OSCILLATOR FREQUENCIES (SEE TEXT)
A SERIES RESISTOR MAY BE REQUIRED IN ORDER TO
LIMIT CRYSTAL DRIVE LEVELS. THIS IS PARTICULARLY
IMPORTANT FOR LOW FREQUENCY CRYSTALS (SEE TEXT).
Figure 16. Using the Crystal Oscillator
SU01539
87LPC760
X2
X1
THE OSCILLATOR MUST BE CONFIGURED IN
THE EXTERNAL CLOCK INPUT MODE.
A CLOCK OUTPUT MAY BE OBTAINED ON
THE X2 PIN BY SETTING THE ENCLK BIT IN
THE P2M1 REGISTER.
CMOS COMPATIBLE EXTERNAL
OSCILLATOR SIGNAL
Figure 17. Using an External Clock Input
Philips Semiconductors Preliminary data
P87LPC760
Low power, low price, low pin count (14 pin)
microcontroller with 1 kbyte OTP
2002 Mar 07
23
SU01167
CLOCK SELECT
CLOCK
SOURCES
CLOCK
OUT
XTAL
SELECT
INTERNAL RC OSCILLATOR
CRYSTAL: LOW FREQUENCY
CRYSTAL: MEDIUM FREQUENCY
CRYSTAL: HIGH FREQUENCY
EXTERNAL CLOCK INPUT
10-BIT RIPPLE COUNTER
RESET
COUNT
COUNT 256
COUNT 1024
OSCILLATOR STARTUP TIMER
DIVIDE-BY-M
(DIVM REGISTER)
AND
CLKR SELECT
CPU
CLOCK
÷1/÷2
CLKR
(UCFG1.3)
POWER DOWN
POWER MONITOR RESET
FOSC0 (UCFG1.0)
FOSC1 (UCFG1.1)
FOSC2 (UCFG1.2)
Figure 18. Block Diagram of Oscillator Control
CPU Clock Modification: CLKR and DIVM
For backward compatibility, the CLKR configuration bit allows setting
the P87LPC760 instruction and peripheral timing to match standard
80C51 timing by dividing the CPU clock by two. Default timing for
the P87LPC760 is 6 CPU clocks per machine cycle while standard
80C51 timing is 12 clocks per machine cycle. This division also
applies to peripheral timing, allowing 80C51 code that is oscillator
frequency and/or timer rate dependent. The CLKR bit is located in
the EPROM configuration register UCFG1, described under EPROM
Characteristics
In addition to this, the CPU clock may be divided down from the
oscillator rate by a programmable divider, under program control.
This function is controlled by the DIVM register. If the DIVM register
is set to zero (the default value), the CPU will be clocked by either
the unmodified oscillator rate, or that rate divided by two, as
determined by the previously described CLKR function.
When the DIVM register is set to some value N (between 1 and
255), the CPU clock is divided by 2 * (N + 1). Clock division values
from 4 through 512 are thus possible. This feature makes it possible
to temporarily run the CPU at a lower rate, reducing power
consumption, in a manner similar to Idle mode. By dividing the clock,
the CPU can retain the ability to respond to events other than those
that can cause interrupts (i.e. events that allow exiting the Idle
mode) by executing its normal program at a lower rate. This can
allow bypassing the oscillator startup time in cases where Power
Down mode would otherwise be used. The value of DIVM may be
changed by the program at any time without interrupting code
execution.
Power Monitoring Functions
The P87LPC760 incorporates power monitoring functions designed
to prevent incorrect operation during initial power up and power loss
or reduction during operation. This is accomplished with two
hardware functions: Power-On Detect and Brownout Detect.
Brownout Detection
The Brownout Detect function allows preventing the processor from
failing in an unpredictable manner if the power supply voltage drops
below a certain level. The default operation is for a brownout
detection to cause a processor reset, however it may alternatively
be configured to generate an interrupt by setting the BOI bit in the
AUXR1 register (AUXR1.5).
The P87LPC760 allows selection of two Brownout levels: 2.5 V or
3.8 V. When V
DD
drops below the selected voltage, the brownout
detector triggers and remains active until V
DD
is returns to a level
above the Brownout Detect voltage. When Brownout Detect causes
a processor reset, that reset remains active as long as V
DD
remains
below the Brownout Detect voltage. When Brownout Detect
generates an interrupt, that interrupt occurs once as V
DD
crosses
from above to below the Brownout Detect voltage. For the interrupt
to be processed, the interrupt system and the BOI interrupt must
both be enabled (via the EA and EBO bits in IEN0).
When Brownout Detect is activated, the BOF flag in the PCON
register is set so that the cause of processor reset may be
determined by software. This flag will remain set until cleared by
software.
Philips Semiconductors Preliminary data
P87LPC760
Low power, low price, low pin count (14 pin)
microcontroller with 1 kbyte OTP
2002 Mar 07
24
For correct activation of Brownout Detect, the V
DD
fall time must be
no faster than 50 mV/µs. When V
DD
is restored, is should not rise
faster than 2 mV/µs in order to insure a proper reset.
The brownout voltage (2.5 V or 3.8 V) is selected via the BOV bit in
the EPROM configuration register UCFG1. When unprogrammed
(BOV = 1), the brownout detect voltage is 2.5 V. When programmed
(BOV = 0), the brownout detect voltage is 3.8 V.
If the Brownout Detect function is not required in an application, it
may be disabled, thus saving power. Brownout Detect is disabled by
setting the control bit BOD in the AUXR1 register (AUXR1.6).
Power On Detection
The Power On Detect has a function similar to the Brownout Detect,
but is designed to work as power comes up initially, before the
power supply voltage reaches a level where Brownout Detect can
work. When this feature is activated, the POF flag in the PCON
register is set to indicate an initial power up condition. The POF flag
will remain set until cleared by software.
Power Reduction Modes
The P87LPC760 supports Idle and Power Down modes of power
reduction.
Idle Mode
The Idle mode leaves peripherals running in order to allow them to
activate the processor when an interrupt is generated. Any enabled
interrupt source or Reset may terminate Idle mode. Idle mode is
entered by setting the IDL bit in the PCON register (see Figure 19).
Power Down Mode
The Power Down mode stops the oscillator in order to absolutely
minimize power consumption. Power Down mode is entered by
setting the PD bit in the PCON register (see Figure 19).
The processor can be made to exit Power Down mode via Reset or
one of the interrupt sources shown in Table 5. This will occur if the
interrupt is enabled and its priority is higher than any interrupt
currently in progress.
In Power Down mode, the power supply voltage may be reduced to
the RAM keep-alive voltage V
RAM
. This retains the RAM contents at
the point where Power Down mode was entered. SFR contents are
not guaranteed after V
DD
has been lowered to V
RAM
, therefore it is
recommended to wake up the processor via Reset in this case. V
DD
must be raised to within the operating range before the Power Down
mode is exited. Since the watchdog timer has a separate oscillator, it
may reset the processor upon overflow if it is running during Power
Down.
Note that if the Brownout Detect reset is enabled, the processor will
be put into reset as soon as V
DD
drops below the brownout voltage.
If Brownout Detect is configured as an interrupt and is enabled, it will
wake up the processor from Power Down mode when V
DD
drops
below the brownout voltage.
When the processor wakes up from Power Down mode, it will start
the oscillator immediately and begin execution when the oscillator is
stable. Oscillator stability is determined by counting 1024 CPU
clocks after start-up when one of the crystal oscillator configurations
is used, or 256 clocks after start-up for the internal RC or external
clock input configurations.
Some chip functions continue to operate and draw power during
Power Down mode, increasing the total power used during Power
Down. These include the Brownout Detect, Watchdog Timer, and
Comparator.
BIT SYMBOL FUNCTION
PCON.7 SMOD1 When set, this bit doubles the UART baud rate for modes 1, 2, and 3.
PCON.6 SMOD0 This bit selects the function of bit 7 of the SCON SFR. When 0, SCON.7 is the SM0 bit. When 1,
SCON.7 is the FE (Framing Error) flag.
1
PCON.5 BOF Brown Out Flag. Set automatically when a brownout reset or interrupt has occurred. Also set at
power on. Cleared by software. Refer to the Power Monitoring Functions section for additional
information.
PCON.4 POF Power On Flag. Set automatically when a power-on reset has occurred. Cleared by software. Refer
to the Power Monitoring Functions section for additional information.
PCON.3 GF1 General purpose flag 1. May be read or written by user software, but has no effect on operation.
PCON.2 GF0 General purpose flag 0. May be read or written by user software, but has no effect on operation.
PCON.1 PD Power Down control bit. Setting this bit activates Power Down mode operation. Cleared when the
Power Down mode is terminated (see text).
PCON.0 IDL Idle mode control bit. Setting this bit activates Idle mode operation. Cleared when the Idle mode is
terminated (see text).
IDL
SU01540
PDGF0GF1POFBOFSMOD0SMOD1
01234567
PCON
Reset Value: S 30h for a Power On reset
S 20h for a Brownout reset
S 00h for other reset sources
Not Bit Addressable
Address: 87h
1. See Figure 31 for additional information.
Figure 19. Power Control Register (PCON)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P56

P87LPC760BN,112

Mfr. #:
Buy P87LPC760BN,112
Manufacturer:
NXP Semiconductors
Description:
IC MCU 8BIT 1KB OTP 14DIP
Lifecycle:
New from this manufacturer.
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