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Operating Limits
The Typical Maximum Q vs Clock Frequency and Band-
pass Gain Error graphs, under Typical Performance Char-
acteristics, define an upper limit of operating Q for each
LTC1264 2nd order section. These graphs indicate the
power supply, f
CLK
and Q value conditions under which a
filter implemented with an LTC1264 will remain stable
when operated at temperatures of 85°C or less. For a 2nd
order section, a bandpass gain error of 3dB or less is
arbitrarily defined as a condition for stability.
When the passband gain error begins to exceed 1dB, the
use of capacitor C
C
will reduce the gain error (capacitor C
C
is connected from the lowpass node to the inverting node
of a 2nd order section). Please refer to Figures 4 through
9. The value of C
C
can be best determined experimentally,
and as a guide it should be about 5pF for each 1dB of gain
error and not to exceed 15pF. When operating LTC1264
very near the limits defined by the Typical Performance
Characteristics graphs, passband gain variations of 2dB
or more should be expected.
Speed Limitations
To avoid op amp slew rate limiting, the signal amplitude
should be kept below a specified level as shown in Table 2.
Table 2. Maximum V
IN
vs V
S
and Clock
V
S
MAXIMUM CLOCK MAXIMUM V
IN
±7.5V 4MHz to 5MHz 0.5V
RMS
f
IN
400kHz
±5V 3MHz to 4MHz 0.5V
RMS
f
IN
250kHz
Single 5V 1MHz to 2MHz 0.35V
RMS
f
IN
160kHz
Clock Feedthrough
Clock feedthrough is defined as the RMS value of the clock
frequency and its harmonics that are present at the filter’s
output pins. The clock feedthrough is tested with the
filter’s input grounded and it depends on PC board layout
and on the value of the power supplies. With proper layout
techniques, the typical values of clock feedthrough are
listed under Electrical Characteristics.
Any parasitic switching transients during the rise and fall
edges of the incoming clock are not part of the clock
feedthrough specifications. Switching transients have fre-
quency contents much higher than the applied clock; their
amplitude strongly depends on scope probing techniques
as well as grounding and power supply bypassing. The
clock feedthrough, if bothersome, can be greatly reduced
by adding a simple RC lowpass network at the final filter
output. This RC will completely eliminate any switching
transients.
Wideband Noise
The wideband noise of the filter is the total RMS value of
the device’s noise spectral density and it is used to
determine the operating signal-to-noise ratio. Most of its
frequency contents lie within the filter passband and it
cannot be reduced with post filtering.
The total wideband noise (µV
RMS
) is nearly independent of
the value of the clock. The clock feedthrough specifica-
tions are not part of the wideband noise.
For a specific filter design, the total noise depends on the
Q of each section and the cascade sequence. Table 3
shows typical 2nd order section noise (gain = 1) for Q
values and supplies operating at 25°C. Noise increases by
20% at the highest operating temperatures.
Table 3. 2nd Order Section Noise (µV
RMS
) for Modes 1, 1b,
2 or 3 (R2 = R4)
QV
S
= ±2.5V V
S
= ±5V V
S
= ±7.5V
140µV
RMS
50 60
250µV
RMS
60 75
360µV
RMS
75 95
475µV
RMS
90 115
590µV
RMS
110 135
Aliasing
Aliasing is an inherent phenomenon of switched-capacitor
filters and it occurs when the frequency of input signals
approaches the sampling frequency. The input signals
that produce the strongest aliased components have a
frequency, f
IN
, such as (f
SAMPLING
– f
IN
) falls into the
filter’s passband. For the LTC1264 the sampling fre-
quency is twice f
CLK
. If the input signal spectrum is not
band-limited, aliasing may occur.
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For example, for an LTC1264 bandpass filter with f
CENTER
= 100kHz and f
CLK
= 2MHz, a 3.9MHz, 10mV input will
produce a 100kHz, 10mV output. A 1st or 2nd order
prefilter will reduce aliasing to acceptable levels in most
cases.
A GUIDE TO BANDPASS DESIGN
Filter design tools like FCAD require design specification
inputs such as passband ripple, attenuation, passband
width and stopband width in order to calculate filter
parameters f
O
, Q, f
n
or poles and zeroes. The results of
these filter approximations most often require Q values
which make excessive demands on the gain-bandwidth
products of active filter realizations. The active filter de-
signer should define a gain response so that the filter’s
mathematical approximation has practical requirements.
Table 4 is a guide to practical design specifications for
realizing bandpass filters with LTC1264 (please also refer
to the Typical Maximum Q vs Clock Frequency and Band-
pass Gain Error graphs under Typical Performance Char-
acteristics).
A Bandpass Design Example
Filter Type: Bandpass
Filter Response: Butterworth
Passband Ripple: 3dB
Attenuation: 60dB
Center Frequency: 40kHz (f
CENTER
)
Passband Width: 10kHz
Stopband Width: 60kHz
Implementing the Bandpass Design
With the LTC1264 in Mode 1b, Butterworth and Chebyshev
bandpass designs with f
CLK
to f
CENTER
ratios greater than
20:1 are possible.
First choose the clock frequency which in Mode 1b must
be greater than 20 times the bandpass center frequency of
40kHz. For this example, let’s choose f
CLK
to be 1MHz.
Table 6 lists the resistors for for the bandpass design
example and Figure 11 shows the complete circuit.
Table 4. Bandpass Design Specifications (f
CENTER
is center
frequency of passband.)
PASSBAND PASSBAND STOPBAND ATTENU-
RIPPLE WIDTH WIDTH ATION
(dB) (Hz) (Hz) (dB)
3dB for Butterworth f
CENTER
/20 5 × Passband 40 to –60
0.1 for Chebyshev f
CENTER
/20 5 × Passband 40 to –60
Note: Reducing passband ripple or attenuation will decrease Q values. The
filter order may also increase.
Table 5. Calculated Filter Parameters
STAGE f
O
Q
1 38.1201kHz 4.3346
2 41.9726kHz 4.3346
3 35.6418kHz 10.5221
4 44.8911kHz 10.5221
Table 6. Calculated Mode 1b Resistors to Nearest 1% Value
Using Table 5 Filter Parameters and Figure 10 Equations
STAGE R1 R2 R3 R5 R6
1 52.3k 10k 56.2k 5k 6.98k
2 47.5k 10k 51.1k 5k 11.8k
3 56.2k 10k 147k 5k 5.11k
4 44.2k 10k 118k 5k 20.5k
Figure 10. Equations for Resistors in Mode 1b Operation
R2 = 10k
R5 = 5k
f
i
=
R1 = (FOR BANDPASS)
R6 =
H
OBP
= + 1
R3 =
R3
H
OBP
R5•f
O
2
f
i
2
f
O
2
()
()
Q
2
f
O
f
CENTER
f
CENTER
f
O
()
2
R2•Q
R6
R6 + 5
()
1264 F10
f
CLK
20
12
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first stage and decreasing the R1 resistor of the last stage
by the same amount (multiplying the R1 resistor of the
first stage and dividing the R1 resistor of the last stage by
2 for narrowband filter, and by 5 for wideband filter is a
good rule of thumb). This adjustment may, however,
increase the filter’s passband noise.
Figure 11. Mode 1b Bandpass Filter
Figures 12 and 13 show the gain response graphs of the
40kHz Butterworth bandpass design described above. The
passband gain response graph (Figure 12) shows a 40kHz
gain of – 0.4dB and a tilted passband from 37kHz to 43kHz.
These errors are due to the 1% resistors used and the side-
to-side matching of the LTC1264 f
CLK
-to-f
CENTER
ratio
which typically is 0.4%. To adjust for 0dB gain at 40kHz,
reduce the value of R1 in the first stage by 5%. To adjust
for a flat passband, adjust by ±1% the value of R6 in stages
3 and 4. Adjusting R6 compensates for the side-to-side
matching errors. Please refer to Figure 5 equations defin-
ing f
O
and Q as a function of R6.
The sequence of 2nd order stages and the bandpass gain
H
OBP
of each stage will determine the gain peaks at the
filter’s intermediate outputs. A given internal output can
have several dB more gain than the final filter output. Gain
peaks occur around the corners of the passband. The gain
peaks can be reduced by increasing the R1 resistor of the
Figure 12. Passband Gain vs Frequency
40kHz Butterworth Bandpass
FREQUENCY (kHz)
30
GAIN (dB)
1.0
0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
46
1264 F12
34
38
42
50
32
36 40
44
48
MODE 1b
V
S
= ±7.5V
f
CLK
= 1MHz
f
CLK
/f
CENTER
= 25:1
Figure 13. Gain vs Frequency
40kHz Butterworth Bandpass
FREQUENCY (kHz)
10
GAIN (dB)
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
74
1264 F13
26
42
58
90
18
34 50
66
82
MODE 1b
V
S
= ±7.5V
f
CLK
= 1MHz
f
CLK
/f
CENTER
= 25:1
R1
R2
R1
R2
IN
1264 F11
OUT
INV B
HPB/NB
BPB
LPB
SB
AGND
V
+
SA
LPA
BPA
HPA/NA
INV A
INV C
HPC/NC
BPC
LPC
SC
V
CLK
SD
LPD
BPD
HPD/ND
INV D
R3
R3
R1
R2
R2
R3
R1
LTC1264
R5
R6
R6
R5
f
CLK
R3
R5
R6
R5
R6
STAGE 2
STAGE 4
STAGE 3
STAGE 1

LTC1264CSW#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Active Filter Hi Speed, 4x Universal Filt Building Blo
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