4
FN6294.4
December 8, 2015
Absolute Maximum Ratings Thermal Information
Supply Voltage, V
DD,
V
HB
- V
HS
(Notes 1, 2) . . . . . . . -0.3V to 18V
LI and HI Voltages (Note 2) . . . . . . . . . . . . . . . -0.3V to V
DD
+ 0.3V
Voltage on LO (Note 2) . . . . . . . . . . . . . . . . . . -0.3V to V
DD
+ 0.3V
Voltage on HO (Note 2) . . . . . . . . . . . . . . V
HS
- 0.3V to V
HB
+ 0.3V
Voltage on HS (Continuous) (Note 2) . . . . . . . . . . . . . . -1V to 110V
Voltage on HB (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118V
Average Current in V
DD
to HB Diode . . . . . . . . . . . . . . . . . . 100mA
Maximum Recommended Operating Conditions
Supply Voltage, V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9V to 14V
Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V
Voltage on HS . . . . . . . . . . . . . . .(Repetitive Transient) -5V to 105V
Voltage on HB . . V
HS
+ 8V to V
HS
+ 14V and V
DD
- 1V to V
DD
+ 100V
HS Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50V/ns
Thermal Resistance (Typical)
JA
(°C/W)
JC
(°C/W)
DFN (Notes 3, 4) . . . . . . . . . . . . . . . . . 47 3.5
SOIC (Note 3) . . . . . . . . . . . . . . . . . . . 120 N/A
Max Power Dissipation at +25°C in Free Air (DFN, Note 3) . . . 2.27W
Storage Temperature Range . . . . . . . . . . . . . . . . . . -65°C to +150°C
For Recommended soldering conditions see Tech Brief TB389.
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. The ISL2100A-ISL2101A are capable of derated operation at supply voltages exceeding 14V. Figure 22 shows the high-side voltage derating
curve for this mode of operation.
2. All voltages referenced to V
SS
unless otherwise specified.
3.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.
4. For
JC,
the “case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379 for details.
Electrical Specifications V
DD
= V
HB
= 12V, V
SS
= V
HS
= 0V, No Load on LO or HO, Unless Otherwise Specified. Parameters with MIN
and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
PARAMETERS SYMBOL TEST CONDITIONS
T
J
= +25°C
T
J
= -40°C to
+125°C
UNITSMIN TYP MAX MIN MAX
SUPPLY CURRENTS
V
DD
Quiescent Current I
DD
ISL2100A; LI = HI = 0V - 0.1 0.25 - 0.3 mA
V
DD
Quiescent Current I
DD
ISL2101A; LI = HI = 0V - 0.3 0.45 - 0.55 mA
V
DD
Operating Current I
DDO
ISL2100A; f = 500kHz - 1.6 2.2 - 2.7 mA
V
DD
Operating Current I
DDO
ISL2101A; f = 500kHz - 1.9 2.5 - 3 mA
Total HB Quiescent Current I
HB
LI = HI = 0V - 0.1 0.15 - 0.2 mA
Total HB Operating Current I
HBO
f = 500kHz - 2.0 2.5 - 3 mA
HB to V
SS
Current, Quiescent I
HBS
LI = HI = 0V; V
HB
= V
HS
= 114V - 0.05 1 - 10 µA
HB to V
SS
Current, Operating I
HBSO
f = 500kHz; V
HB
= V
HS
= 114V - 0.9 - - - mA
INPUT PINS
Low Level Input Voltage Threshold V
IL
ISL2100A 3.7 4.4 - 2.7 - V
Low Level Input Voltage Threshold V
IL
ISL2101A 1.4 1.8 - 1.2 - V
High Level Input Voltage Threshold V
IH
ISL2100A - 6.6 7.4 - 8.4 V
High Level Input Voltage Threshold V
IH
ISL2101A - 1.8 2.2 - 2.4 V
Input Voltage Hysteresis V
IHYS
ISL2100A - 2.2 - - - V
Input Pull-down Resistance R
I
- 210 - 100 500 k
UNDERVOLTAGE PROTECTION
V
DD
Rising Threshold V
DDR
6.8 7.3 7.8 6.5 8.1 V
V
DD
Threshold Hysteresis V
DDH
-0.6- - - V
HB Rising Threshold V
HBR
6.2 6.9 7.5 5.9 7.8 V
ISL2100A, ISL2101A
5
FN6294.4
December 8, 2015
HB Threshold Hysteresis V
HBH
-0.6- - - V
BOOTSTRAP DIODE
Low Current Forward Voltage V
DL
I
VDD-HB
= 100µA - 0.5 0.6 - 0.7 V
High Current Forward Voltage V
DH
I
VDD-HB
= 100mA - 0.7 0.9 - 1 V
Dynamic Resistance R
D
I
VDD-HB
= 100mA - 0.8 1 - 1.5
LO GATE DRIVER
Low Level Output Voltage V
OLL
I
LO
= 100mA - 0.25 0.3 - 0.4 V
High Level Output Voltage V
OHL
I
LO
= -100mA,
V
OHL
= V
DD
- V
LO
- 0.25 0.3 - 0.4 V
Peak Pull-Up Current I
OHL
V
LO
= 0V - 2 - - - A
Peak Pull-Down Current I
OLL
V
LO
= 12V - 2 - - - A
HO GATE DRIVER
Low Level Output Voltage V
OLH
I
HO
= 100mA - 0.25 0.3 - 0.4 V
High Level Output Voltage V
OHH
I
HO
= -100mA,
V
OHH
= V
HB
- V
HO
- 0.25 0.3 - 0.4 V
Peak Pull-Up Current I
OHH
V
HO
= 0V - 2 - - - A
Peak Pull-Down Current I
OLH
V
HO
= 12V - 2 - - - A
Electrical Specifications V
DD
= V
HB
= 12V, V
SS
= V
HS
= 0V, No Load on LO or HO, Unless Otherwise Specified. Parameters with MIN
and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested. (Continued)
PARAMETERS SYMBOL TEST CONDITIONS
T
J
= +25°C
T
J
= -40°C to
+125°C
UNITSMIN TYP MAX MIN MAX
Electrical Specifications Switching Specifications V
DD
= V
HB
= 12V, V
SS
= V
HS
= 0V, No Load on LO or HO, Unless Otherwise
Specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified.
Temperature limits established by characterization and are not production tested.
PARAMETERS SYMBOL
TEST
CONDITIONS
T
J
= +25°C
T
J
= -40°C
to +125°C
UNITSMIN TYP MAX MIN MAX
Lower Turn-Off Propagation Delay (LI Falling to LO Falling) t
LPHL
- 34 50 - 60 ns
Upper Turn-Off Propagation Delay (HI Falling to HO Falling) t
HPHL
- 31 50 - 60 ns
Lower Turn-On Propagation Delay (LI Rising to LO Rising) t
LPLH
- 39 50 - 60 ns
Upper Turn-On Propagation Delay (HI Rising to HO Rising) t
HPLH
- 39 50 - 60 ns
Delay Matching: Upper Turn-Off to Lower Turn-On t
MON
1 8 - - 16 ns
Delay Matching: Lower Turn-Off to Upper Turn-On t
MOFF
1 6 - - 16 ns
Either Output Rise/Fall Time (10% to 90%/90% to 10%) t
RC,
t
FC
C
L
= 1nF - 10 - - - ns
Either Output Rise/Fall Time (3V to 9V/9V to 3V) t
R,
t
F
C
L
= 0.1µF - 0.5 0.6 - 0.8 us
Minimum Input Pulse Width that Changes the Output t
PW
----50ns
Bootstrap Diode Turn-On or Turn-Off Time t
BS
-10- - - ns
ISL2100A, ISL2101A
6
FN6294.4
December 8, 2015
Timing Diagrams
Pin Descriptions
SYMBOL DESCRIPTION
V
DD
Positive supply to lower gate driver. Bypass this pin to V
SS
.
HB High-side bootstrap supply. External bootstrap capacitor is required. Connect positive side of bootstrap capacitor to this pin.
Bootstrap diode is on-chip.
HO High-side output. Connect to gate of high-side power MOSFET.
HS High-side source connection. Connect to source of high-side power MOSFET. Connect negative side of bootstrap capacitor to this
pin.
HI High-side input.
LI Low-side input.
V
SS
Chip negative supply, which will generally be ground.
LO Low-side output. Connect to gate of low-side power MOSFET.
EPAD Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other pins.
FIGURE 3. PROPAGATION DELAYS
FIGURE 4. DELAY MATCHING
t
HPLH
,
t
LPLH
t
HPHL
,
t
LPHL
HI,
LI
HO,
LO
t
MON
t
MOFF
LI
HI
LO
HO
Typical Performance Curves
FIGURE 5. ISL2100A IDD OPERATING CURRENT vs
FREQUENCY
FIGURE 6. ISL2101A IDD OPERATING CURRENT vs
FREQUENCY
10 100 1
.
10
3
0.1
1
10
FREQUENCY (kHz)
IDDO (mA)
T = -40°C
T = +25°C
T = +125°C
T = +150°C
10 100 1
.
10
3
0.1
1
10
FREQUENCY (kHz)
IDDO (mA)
T = -40°C
T = +25°C
T = +150°C
T = +125°C
ISL2100A, ISL2101A

ISL2101AABZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Gate Drivers 100V/2A H-BRDG DRVR 8LD
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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