74ACTQ573QSC

© 2000 Fairchild Semiconductor Corporation DS010633 www.fairchildsemi.com
January 1990
Revised October 2000
74ACQ573 • 74ACTQ573 Quiet Series
Octal Latch with 3-STATE Outputs
74ACQ573 74ACTQ573
Quiet Series
Octal Latch with 3-STATE Outputs
General Description
The ACQ/ACTQ573 is a high-speed octal latch with buff-
ered common Latch Enable (LE) and buffered common
Output Enable (OE
) inputs. The ACQ/ACTQ573 is func-
tionally identical to the ACQ/ACTQ373 but with inputs and
outputs on opposite sides of the package. The ACQ/ACTQ
utilizes Fairchild’s Quiet Series
technology to guarantee
quiet output switching and improved dynamic threshold
performance. FACT Quiet Series
features GTO output
control and undershoot corrector in addition to a split
ground bus for superior performance.
Features
I
CC
and I
OZ
reduced by 50%
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Guaranteed pin-to-pin skew AC performance
Improved latch-up immunity
Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
Outputs source/sink 24 mA
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
FACT, Quiet Series, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation
Order Number Package Number Package Description
74ACQ573SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACQ573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACQ573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACQ573PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74ACTQ573SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACTQ573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACTQ573QSC MQA20 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150 Wide
74ACTQ573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACTQ573PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description
D
0
D
7
Data Inputs
LE Latch Enable Input
OE
3-STATE Output Enable Input
O
0
O
7
3-STATE Latch Outputs
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74ACQ573 74ACTQ573
Functional Description
The ACQ/ACTQ573 contains eight D-type latches with 3-
STATE output buffers. When the Latch Enable (LE) input is
HIGH, data on the D
n
inputs enters the latches. In this con-
dition the latches are transparent, i.e., a latch output will
change state each time its D-type input changes. When LE
is LOW the latches store the information that was present
on the D-type inputs at setup time preceding the
HIGH-to-LOW transition of LE. The 3-STATE buffers are
controlled by the Output Enable (OE
) input. When OE is
LOW, the buffers are enabled. When OE
is HIGH the buff-
ers are in the high impedance mode but this does not inter-
fere with entering new data into the latches.
Truth Table
H = HIGH Voltage
L = LOW Voltage
Z = High Impedance
X = Immaterial
O
0
= Previous O
0
before HIGH-to-LOW transition of Latch Enable
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs Outputs
OE
LE D
O
n
LHH H
LHL L
LLX O
0
HXX Z
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74ACQ573 74ACTQ573
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for ACQ
Supply Voltage (V
CC
) 0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= 0.5V 20 mA
V
I
= V
CC
+ 0.5V +20 mA
DC Input Voltage (V
I
) 0.5V to V
CC
+ 0.5V
DC Output Diode Current (I
OK
)
V
O
= 0.5V 20 mA
V
O
= V
CC
+ 0.5V +20 mA
DC Output Voltage (V
O
) 0.5V to V
CC
+ 0.5V
DC Output Source
or Sink Current (I
O
) ±50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
) ±50 mA
Storage Temperature (T
STG
) 65°C to +150°C
DC Latchup Source
or Sink Current ±300 mA
Junction Temperature (T
J
)
PDIP 140
°C
Supply Voltage (V
CC
)
ACQ 2.0V to 6.0V
ACTQ 4.5V to 5.5V
Input Voltage (V
I
)0V to V
CC
Output Voltage (V
O
)0V to V
CC
Operating Temperature (T
A
) 40°C to +85°C
Minimum Input Edge Rate
V/t
ACQ Devices
V
IN
from 30% to 70% of V
CC
V
CC
@ 3.0V, 4.5V, 5.5V 125 mV/ns
Minimum Input Edge Rate
V/t
ACTQ Devices
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V 125 mV/ns
Symbol Parameter
V
CC
T
A
= +25°CT
A
= 40°C to +85°C
Units Conditions
(V) Typ Guaranteed Limits
V
IH
Minimum HIGH Level 3.0 1.5 2.1 2.1 V
OUT
= 0.1V
Input Voltage 4.5 2.25 3.15 3.15 V or V
CC
0.1V
5.5 2.75 3.85 3.85
V
IL
Maximum LOW Level 3.0 1.5 0.9 0.9 V
OUT
= 0.1V
Input Voltage 4.5 2.25 1.35 1.35 V or V
CC
0.1V
5.5 2.75 1.65 1.65
V
OH
Minimum HIGH Level 3.0 2.99 2.9 2.9
Output Voltage 4.5 4.49 4.4 4.4 V I
OUT
= 50 µA
5.55.495.4 5.4
V
IN
= V
IL
or V
IH
3.0 2.56 2.46 I
OH
= 12 mA
4.5 3.86 3.76 V I
OH
= 24 mA
5.5 4.86 4.76 I
OH
= 24 mA (Note 2)
V
OL
Maximum LOW Level 3.0 0.002 0.1 0.1
Output Voltage 4.5 0.001 0.1 0.1 V I
OUT
= 50 µA
5.5 0.001 0.1 0.1
V
IN
= V
IL
or V
IH
3.0 0.36 0.44 I
OL
= 12 mA
4.5 0.36 0.44 V I
OL
= 24 mA
5.5 0.36 0.44 I
OL
= 24 mA (Note 2)
I
IN
(Note 4) Maximum Input Leakage Current 5.5 ± 0.1 ± 1.0 µAV
I
= V
CC
, GND
I
OLD
Minimum Dynamic 5.5 75 mA V
OLD
= 1.65 V
Max
I
OHD
Output Current (Note 3) 5.5 75 mA V
OHD
= 3.85 V
Min
I
CC
(Note 4) Maximum Quiescent Supply Current 5.5 4.0 40.0 µAV
IN
= V
CC
or GND
I
OZ
Maximum 3-STATE V
I
(OE) = V
IL
, V
IH
Leakage Current 5.5 ±0.25 ±2.5 µAV
I
= V
CC
, GND
V
O
= V
CC
, GND
V
OLP
Quiet Output
5.0 1.1 1.5 V
Figures 1, 2
Maximum Dynamic V
OL
(Note 5)(Note 6)

74ACTQ573QSC

Mfr. #:
Manufacturer:
ON Semiconductor / Fairchild
Description:
Latches Octal Latch
Lifecycle:
New from this manufacturer.
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