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SP6330EK1-L-X-J-C

P1-P3P4-P6P7-P9P10-P12P13-P13
Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family © Copyright 2006 Sipex Corporation
7
Figure 1: Functionality of a SP63XX family member with manual reset and watchdog
capabilities but without WDOB output.
• V1 > Vth1, V2 > Vth2 , V3 > Vth3 and V4 > Vth4 (all supplies over their corresponding
thresholds)---> RSTB is de-asserted after reset timeout period (Trp).
• MRIB goes to “LOW” to force “Reset” ----> RSTB is asserted immediately.
• WDI does not make any transition during watchdog timeout period (Twd) ---->RSTB is
asserted for a duration of reset timeout period (Trp).
• One of the supplies drops below its corresponding threshold (in this case V3)---->RSTB
is asserted immediately.
THEORY OF OPERATION
V1
V2
V3
V4
Vth1
Vth2
Vth3=0.5V
Vth4=0.5V
MRIB
WDI
RSTB
Trp
Trp
Twd
Trp
T<Twd
T<Twd
T<Twd T<Twd
T<Twd
Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family © Copyright 2006 Sipex Corporation
8
V1
RSTB
ResetB Timeout Delay
APPLICATION INFORMATION
RSTB
WDI = GND, V1=V2=V3=V4=5V,
MRIB = open.
Watchdog Timeout Period = 1.52S
Watchdog Timeout Period
Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family © Copyright 2006 Sipex Corporatio n
9
0
100
200
300
400
500
85 80 70 60 50 40 30 20 10 0 -10 -20 -30 -40
D e g C
R
e
s
e
t
T
i
m
e
o
u
t
(
m
S
e
c
)
Reset Timeout vs. Temperature
ResetTimeout Delay Vs. Temperature
R S T B v s . V 1 (V 2 = G N D )
0
0.5
1
1.5
2
2.5
3
3
.
5
4
4.5
5
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
V1 (Vdc)
RS T B (V o lt s DC)
Reset Good
APPLICATION INFORMATION
(400ms Reset)
P1-P3P4-P6P7-P9P10-P12P13-P13

SP6330EK1-L-X-J-C

Mfr. #:
Buy SP6330EK1-L-X-J-C
Manufacturer:
MaxLinear
Description:
Supervisory Circuits Quad microPower Supervisory Circuits
Lifecycle:
New from this manufacturer.
Delivery:
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