NCP1201
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10
DETAILED OPERATING DESCRIPTION
Introduction
The NCP1201 implements a standard current mode
architecture where the switch--off time is dictated by the peak
current setpoint. This component represents the ideal
candidate where low part--count is the key criteria,
particularly in low--cost AC--DC adapters, auxiliary supplies
etc. Due to its high--performance High--Voltage technology,
the NCP1201 incorporates all the necessary components
normally needed in UC384X based supplies: timing
components, feedback devices, low--pass filter and
self--supply. This later point emphasizes the fact that
ON Semiconductors NCP1201 does NOT need an auxiliary
winding to operate: the device is self supplied from the
high--voltage rail and delivers a V
CC
to the IC. This system
is named the Dynamic Self--Supply (DSS).
Dynamic Self--Supply
The DSS principle is based on the charge/discharge of the
V
CC
bulk capacitor from a low level up to a higher level. We
can easily describe the current source operation following
simple logic equations:
POWER--ON: IF V
CC
< V
CCOFF
THEN
Current Source is ON, no output pulses
IF VCC decreasing > V
CCON
THEN
Current Source is OFF, output is pulsing
IF VCC increasing < V
CCOFF
THEN
Current Source is ON, output is pulsing
Typical values are: V
CCOFF
= 12.5 V, V
CCON
= 10.5 V
To better understand the operation principle, Figure 27
sketch offers the necessary explanation,
Figure 27. The Charge/Discharge Cycle Over a 10 mFV
CC
Capacitor
10 mS 30 mS 50 mS 70 mS 90 mS
Current
Source
OFF
V
CC
Output Pulses
Vripple=2V
VCC
OFF
= 12.5 V
VCC
ON
= 10.5 V
ON
The DSS behavior actually depends on the internal IC
consumption and the MOSFET’s gate charge Qg. If we
select a MOSFET like the MTP2N60E, Qg max equals
22 nC. With a maximum switching frequency of 70 kHz for
the oscillator 60 kHz, the average power necessary to drive
the MOSFET (excluding the driver efficiency and
neglecting various voltage drops) is:
P
driver
= F
sw(max)
× Q
g
× V
CC
(eq. 1)
Where,
P
driver
= Average Power to drive the MOSFET
F
sw(max)
= Maximum switching frequency
Qg = MOSFET’s gate charge
V
CC
= VGS level applied to the gate of the MOSFET
To obtain an estimation of the driving current, simply
divide Pdriver by V
CC
,
I
driver
= F
sw(max)
× Q
g
= 1.54 mA
(eq. 2)
The total standby power consumption at no--load will
therefore heavily rely on the internal IC current
consumption plus the driving current (altered by the driver’s
efficiency). Suppose that the IC is supplied from a 350 VDC
line. The current flowing through pin 8 is a direct image of
the NCP1201 current consumption (neglecting the
switching losses of the HV current source). If I
CC2
equals
2.1 mA @ T
A
=25C, then the power dissipated (lost) by the
IC is simply: 350 V x 2.1 mA = 735 mW. For design and
reliability reasons, it would be interesting to reduce this
source of wasted power. In order to achieve that, different
methods can be used.
1.UseaMOSFETwithlowergatechargeQg;
2. Connect pin through a diode (1N4007 typically) to
one of the mains input. The average value on pin 8
becomes:
V
mainsPEAK
× 2
π
(eq. 3)
NCP1201
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11
Our power contribution example drops to 223 V x 2.1 m
= 468.3 mW. If a resistor is installed between the mains and
the diode, you further force the dissipation to migrate from
the package to the resistor. The resistor value should be
carefully selected to account for low--line startup.
1
2
3
4
8
7
6
5
Figure 28. A Simple Diode Naturally Reduces the
Average Voltage on Pin 8
Mains
HV
Cbulk
3. Permanently force the V
CC
level above VCC
OFF
with an auxiliary winding. It will automatically
disconnect the internal startup source and the IC
will be fully self--supplied from this winding.
Again, the total power drawn from the mains will
significantly decrease. By using this approach,
user need to make sure the auxiliary voltage never
exceeds the 16 V limit for all line conditions.
Skipping Cycle Mode
The NCP1201 automatically skips switching cycles when
the output power demand drops below a preset level. This is
accomplished by monitoring the FB pin. In normal
operation, FB pin imposes a peak current according to the
load value. If the load demand decreases, the internal loop
asks for less peak current. When this set--point reaches the
skip mode threshold level, 1.07 V, the IC prevents the
current from decreasing further down and starts to blank the
output pulses, i.e. the controller enters the so--called Skip
Cycle Mode, also named Controlled Burst Operation. The
power transfer now depends upon the width of the pulse
bunches, Figure 29.
Suppose we have the following component values:
Lp, primary inductance = 1.0 mH
F
sw
, switching frequency = 60 kHz
I
p
(skip) = 200 mA (or 333 mV/R
sense
)
The theoretical power transfer is therefore:
1
2
× L
p
× I
p
2
× F
sw
= 1.2 W
(eq. 4)
If the controller enters Skip Cycle Mode with a pulse packet
length of 20 ms over a recurrent period of 100 ms, then the
total power transfer reduced to 1.2 W x 0.2 = 240 mW.
To better understand how this Skip Cycle Mode takes
place, a look at the operation mode versus the FB pin voltage
level shown below, immediately gives the necessary insight.
1.07 V
4.2 V, FB Pin Open
FB
Normal Current Mode Operation
Skip Cycle Operation
I
p(min)
= 333 mV / R
sense
Figure 29. Feedback Pin Voltage and Modes of Operation
2.97 V, Upper Dynamic Range
When FB pin voltage level is above the skip cycle threshold
(1.07 V by default), the peak current cannot exceed
0.9 V/R
sense
. When the IC enters the skip cycle mode, the
peak current cannot go below V
SKIP
/3.3. By using the peak
current limit reduction scheme, the skip cycle takes place at
a lower peak current, which guarantees noise free operation.
NCP1201
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Figure 30. MOSFET V
DS
at Various Power Levels, P1<P2<P3
P
1
=0.4W
P
2
=1.8W
P
3
=3.6W
315.4uS
882uS 1.450mS 2.017mS
2.585mS
300.0M
200.0M
100.0M
0
Skip Cycle
current limit
Max peak
current
Figure 31. The Skip Cycle Takes Place at Low Peak Current

NCP1201P100G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC CTRLR PWM CM OTP 8DIP
Lifecycle:
New from this manufacturer.
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