September 1983
Revised February 1999
MM74HC174 Hex D-Type Flip-Flops with Clear
© 1999 Fairchild Semiconductor Corporation DS005318.prf www.fairchildsemi.com
MM74HC174
Hex D-Type Flip-Flops with Clear
General Description
The MM74HC174 edge triggered flip-flops utilize advanced
silicon-gate CMOS technology to implement D-type flip-
flops. They possess high noise immunity, low power, and
speeds comparable to low power Schottky TTL circuits.
This device contains 6 master-slave flip-flops with a com-
mon clock and common clear. Data on the D input having
the specified setup and hold times is transferred to the Q
output on the LOW-to-HIGH transition of the CLOCK input.
The CLEAR input when LOW, sets all outputs to a low
state.
Each output can drive 10 low power Schottky TTL equiva-
lent loads. The MM74HC174 is functionally as well as pin
compatible to the 74LS174. All inputs are protected from
damage due to static discharge by diodes to V
CC
and
ground.
Features
■ Typical propagation delay: 16 ns
■ Wide operating voltage range: 2–6V
■ Low input current: 1 µA maximum
■ Low quiescent current: 80 µA (74HC Series)
■ Output drive: 10 LSTTL loads
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Truth Table
(Each Flip-Flop)
H = HIGH Level (steady state)
L = LOW Level (steady state)
X = Don't Care
↑ = Transition from LOW-to-HIGH level
Q
0
= The level of Q before the indicated steady state input conditions were
established.
Order Number Package Number Package Description
MM74HC174M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC174SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC174MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC174N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Inputs Outputs
Clear Clock D Q
LXXL
H ↑ HH
H ↑ LL
HLXQ
0