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ADP1974ARUZ-R7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
Data Sheet ADP1974
Rev. 0 | Page 3 of 19
SPECIFICATIONS
VIN = 24 V and specifications valid for T
J
= −40°C to +125°C, unless otherwise specified. Typical values are at T
A
= 25°C. All limits at
temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT VOLTAGE (VIN)
Voltage Range V
IN
6 60 V
VIN Supply Current I
VIN
R
FREQ
= 100 kΩ, V
SS
= 0 V, SYNC floating,
FAULT = low, EN = high
1.5 2.5 mA
VIN Shutdown Current I
SHDN
V
EN
= 0 V 15 70 μA
UVLO Threshold Rising V
IN
rising 5.71 6 V
UVLO Threshold Falling V
IN
falling 5.1 5.34 V
SOFT START (SS)
SS Pin Current I
SS
V
SS
= 0 V 4 5 6 μA
SS Threshold Rising Switching enable threshold 0.52 0.65 V
SS Threshold Falling Switching disable threshold 0.4 0.5 V
End of Soft Start Asynchronous to synchronous threshold 4.4 4.5 4.6 V
PWM CONTROL
FREQ
Frequency Range f
SET
R
FREQ
= 33.2 kΩ to 200 kΩ 50 300 kHz
Oscillator Frequency f
OSC
R
FREQ
= 100 kΩ 90 100 110 kHz
FREQ Pin Voltage V
FREQ
R
FREQ
= 100 kΩ 1.2 1.252 1.3 V
SYNC Output (Internal Frequency Control) V
SCFG
≥ 4.53 V or SCFG pin floating
Internal SYNC Range f
SET
For SYNC output 50 300 kHz
SYNC Output Clock Duty Cycle V
SCFG
= V
VREG
, R
FREQ
= 100 kΩ 40 50 60 %
SYNC Sink Resistance R
SYNC
V
SCFG
= 5 V, I
SYNC
= 10 mA 10 20 Ω
SYNC Input (External Frequency Control) V
SCFG
< 4.25 V
External SYNC Range f
SYNC
For SYNC input clock 50 300 kHz
SYNC Pull-Down Resistor 0.5 1 1.5 MΩ
Maximum SYNC Pin Voltage V
SYNC
5.5 V
SYNC Threshold Rising 1.2 1.5 V
SYNC Threshold Falling 0.7 1.05 V
Minimum Pulse Width 100 ns
SCFG V
SCFG
SCFG High Threshold Rising SYNC set to input 4.53 4.7 V
SCFG High Threshold Falling SYNC set to output 4.25 4.51 V
SCFG Low Threshold Rising Programmable phase shift above threshold 0.52 0.65 V
SCFG Low Threshold Falling No phase shift 0.4 0.5 V
SCFG Pin Current I
ISCFG
R
FREQ
= 100 kΩ, V
SCFG
= GND 9.5 11 12.5 μA
DMAX
Maximum Internal Duty Cycle V
COMP
, V
DMAX
, V
SS
, and V
SCFG
= 5 V 97 %
DMAX Setting Current I
DMAX
V
DMAX
= 0 V, R
FREQ
= 100 kΩ 9.5 11 12.5 μA
DMAX and SCFG Current Matching
1
10 %
COMP
COMP Pin Input Voltage Range V
COMP
0 5.0 V
Internal Peak-to-Peak Ramp Voltage V p-p 4 V p-p
Maximum Internal Ramp Voltage 4.5 V
Minimum Internal Ramp Voltage 0.45 0.5 0.55 V
DT
DT Pin Current I
DT
R
FREQ
= 100 kΩ, V
DT
= GND 20 22 μA
Maximum DT Programming Voltage V
DT
3.5 V
ADP1974 Data Sheet
Rev. 0 | Page 4 of 19
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
PRECISION ENABLE LOGIC (EN)
Maximum EN Pin Voltage 60 V
EN Threshold Rising 1.25 1.4 V
EN Threshold Falling 1.1 1.22 V
EN Pin Current V
EN
= 5 V, internal pull down 0.32 2 μA
MODE LOGIC
Maximum MODE Pin Voltage 5.5 V
MODE Threshold Rising 1.20 1.5 V
MODE Threshold Falling 0.7 1.05 V
CURRENT LIMIT (CL)
Set Current I
CL
V
CL
= 0 V 18 20 21 μA
Buck CL Threshold V
CL (BUCK)
250 300 350 mV
Buck Negative Current Threshold V
NC (BUCK)
400 450 500 mV
Boost CL Threshold V
CL (BOOST)
450 500 550 mV
Hiccup Detect Time R
FREQ
= 100 kΩ, 500 consecutive clock pulses 5.2 ms
Hiccup Off Time R
FREQ
= 100 kΩ, 500 consecutive clock pulses 5.2 ms
VREG EN = high
LDO Regulator Output Voltage V
VREG
V
IN
= 6 V to 60 V, no external load 4.9 5 5.1 V
Guaranteed Output Current I
OUT (MAX)
V
IN
= 6 V, external load 5 mA
Load Regulation V
IN
= 6 V, I
OUT
= 0 mA to 5 mA 4.9 5 5.1 V
FAULT
Maximum FAULT Pin Voltage V
FAU LT
60 V
FAULT Threshold Rising 1.2 1.5 V
FAULT Threshold Falling 0.7 1.05 V
FAULT Pin Current V
FAU LT
= 5 V, internal 8.5 MΩ pull-down resistor 0.49 2 μA
PWM DRIVE LOGIC SIGNALS (DH/DL)
DL Drive Voltage V
DL
No load VREG V
DH Drive Voltage V
DH
No load VREG V
DL and DH Sink Resistance I
DL
= 10 mA 1.2 2.4 Ω
DL and DH Source Resistance I
DL
= 10 mA 1.4 2.6 Ω
DL and DH Pull-Down Resistor 0.5 1 1.5 MΩ
THERMAL SHUTDOWN (TSD)
TSD Threshold Rising 150 °C
TSD Threshold Falling 135 °C
1
The DMAX and SCFG current matching specification is calculated by taking the absolute value of the difference between the measured I
SCFG
and I
DMAX
currents, dividing
them by the 11 μA typical value, and multiplying this answer by 100.
100
A11
(%)
DMAXSCFG
II
t MatchingCFG CurrenDMAX and S
Data Sheet ADP1974
Rev. 0 | Page 5 of 19
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
VIN, EN, FAULT to GND −0.3 V to +61 V
SYNC, COMP, MODE, VREG to GND −0.3 V to +5.5 V
DH, DL, SS, DMAX, SCFG, CL, DT,
FREQ to GND
−0.3 V to VREG + 0.3 V
Operating Ambient Temperature Range −40°C to +85°C
Junction Temperature 125°C
Storage Temperature Range −65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Absolute maximum ratings apply individually only, not in
combination.
THERMAL OPERATING RANGES
The ADP1974 can be damaged when the junction temperature
limits are exceeded. The maximum operating junction
temperature (T
J
MAX
) takes precedence over the maximum
operating ambient temperature (T
A
MAX
). Monitoring ambient
temperature does not guarantee that the junction temperature
(T
J
) is within the specified temperature limits.
In applications with high power dissipation and poor printed
circuit board (PCB) thermal resistance, the maximum ambient
temperature may need to be derated. In applications with
moderate power dissipation and low PCB thermal resistance,
the maximum ambient temperature can exceed the maximum
limit when the junction temperature is within specification
limits.
The junction temperature (T
J
) of the device is dependent on the
ambient temperature (T
A
), the power dissipation of the device
(P
D
), and the junction to ambient thermal resistance of the
package (θ
JA
). Use the following equation to calculate the
maximum junction temperature (T
J
) from the ambient
temperature (T
A
) and power dissipation (P
D
):
T
J
= T
A
+ (P
D
× θ
JA
) (1)
For additional information on thermal resistance, refer to
Application Note AN-000, Thermal Characteristics of IC
Assembly.
ESD CAUTION
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

ADP1974ARUZ-R7

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Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Controllers WM Controller for Battery Test Solution
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