MC74AC257DR2G

© Semiconductor Components Industries, LLC, 2015
March, 2015 − Rev. 8
1 Publication Order Number:
MC74AC257/D
MC74AC257, MC74ACT257
Quad 2-Input Multiplexer
with 3-State Outputs
The MC74AC257/74ACT257 is a quad 2−input multiplexer with
3−state outputs. Four bits of data from two sources can be selected
using a Common Data Select input. The four outputs present the
selected data in true (noninverted) form. The outputs may be switched
to a high impedance state by placing a logic HIGH on the common
Output Enable (OE
) input, allowing the outputs to interface directly
with bus−oriented systems.
Multiplexer Expansion by Tying Outputs Together
Noninverting 3−State Outputs
Outputs Source/Sink 24 mA
ACT257 Has TTL Compatible Inputs
These are Pb−Free Devices
1516 14 13 12 11 10
21 34567
V
CC
9
8
OE
I
0c
I
1c
Z
c
I
0d
I
1d
Z
d
SI
0a
I
1a
Z
a
I
0b
I
1b
Z
b
GND
Figure 1. Pinout: 16−Lead Packages Conductors
(Top View)
www.onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
1
16
1
16
MARKING
DIAGRAMS
xxx = AC or ACT
A = Assembly Location
WL or L = Wafer Lot
Y = Year
WW or W = Work Week
G or G = Pb−Free Package
1
16
xxx257G
AWLYWW
xxx
257
ALYWG
G
1
16
(Note: Microdot may be in either location)
MC74AC257, MC74ACT257
www.onsemi.com
2
PIN NAME
PIN FUNCTION
S Common Data Select Input
OE 3−State Output Enable Input
I
0a
−I
0d
Data Inputs from Source 0
I
1a
−I
1d
Data Inputs from Source 1
Z
a
−Z
d
3−State Multiplexer Outputs
TRUTH TABLE
Output
Enable
Select
Input
Data
Inputs
Outputs
OE S I
0
I
1
Z
H X X X Z
L H X LL
L H X HH
L L L XL
L L H X H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Figure 2. Logic Symbol
S
OE I
0a
I
1a
I
0b
I
1b
Z
b
I
0c
I
1c
I
0d
I
1d
Z
a
Z
c
Z
d
FUNCTIONAL DESCRIPTION
The MC74AC257/74ACT257 is a quad 2−input
multiplexer with 3−state outputs. It selects four bits of data
from two sources under control of a Common Data Select
input. When the Select input is LOW, the I
0x
inputs are
selected and when Select is HIGH, the I
1x
inputs are
selected. The data on the selected inputs appears at the
outputs in true (noninverted) form. The device is the logic
implementation of a 4−pole, 2−position switch where the
position of the switch is determined by the logic levels
supplied to the Select input. The logic equations for the
outputs are shown below:
Z
a
= OE(I
1a
S+I
0a
S)
Z
b
= OE(I
1b
S+I
0b
S)
Z
c
= OE(I
1c
S+I
0c
S)
Z
d
= OE(I
1d
S+I
0d
S)
When the Output Enable input (OE
) is HIGH, the outputs
are forced to a high impedance state. If the outputs are tied
together, all but one device must be in the high impedance
state to avoid high currents that would exceed the maximum
ratings. Designers should ensure the Output Enable signals
to 3−state devices whose outputs are tied together are
designed so there is no overlap.
NOTE: This diagram is provided only for the understanding of logic operations
and should not be used to estimate propagation delays.
OE I
0a
I
1a
I
0b
I
1b
I
0c
I
1c
I
0d
I
1d
S
Z
a
Z
b
Z
c
Z
d
Figure 3. Logic Diagram
MC74AC257, MC74ACT257
www.onsemi.com
3
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage −0.5 to +7.0 V
V
I
DC Input Voltage *0.5 V
CC
+0.5 V
V
O
DC Output Voltage (Note 1) *0.5 V
CC
+0.5 V
I
IK
DC Input Diode Current ±20 mA
I
OK
DC Output Diode Current ±50 mA
I
O
DC Output Sink/Source Current ±50 mA
I
CC
DC Supply Current per Output Pin ±50 mA
I
GND
DC Ground Current per Output Pin ±50 mA
T
STG
Storage Temperature Range −65 to +150 °C
T
L
Lead temperature, 1 mm from Case for 10 Seconds 260 °C
T
J
Junction temperature under Bias +150 °C
q
JA
Thermal Resistance (Note 2) SOIC
TSSOP
69.1
103.8
°C/W
P
D
Power Dissipation in Still Air at 65°C (Note 3) SOIC
TSSOP
500
500
mW
MSL Moisture Sensitivity Level 1
F
R
Flammability Rating Oxygen Index: 30% − 35% UL 94 V−0 @ 0.125 in
V
ESD
ESD Withstand Voltage Human Body Model (Note 4)
Machine Model (Note 5)
Charged Device Model (Note 6)
> 2000
> 200
> 1000
V
I
Latch−Up
Latch−Up Performance Above V
CC
and Below GND at 85°C (Note 7) ±100 mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. I
O
absolute maximum rating must be observed.
2. The package thermal impedance is calculated in accordance with JESD51−7.
3. 500 mW at 65°C; derate to 300 mW by 10 mW/ from 65°C to 85°C.
4. Tested to EIA/JESD22−A114−A.
5. Tested to EIA/JESD22−A115−A.
6. Tested to JESD22−C101−A.
7. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Typ Max Unit
V
CC
Supply Voltage
AC 2.0 5.0 6.0
V
ACT 4.5 5.0 5.5
V
IN
, V
OUT
DC Input Voltage, Output Voltage (Ref. to GND) 0 V
CC
V
t
r
, t
f
Input Rise and Fall Time (Note 1)
AC Devices except Schmitt Inputs
V
CC
@ 3.0 V 150
V
CC
@ 4.5 V 40 ns/V
V
CC
@ 5.5 V 25
t
r
, t
f
Input Rise and Fall Time (Note 2)
ACT Devices except Schmitt Inputs
V
CC
@ 4.5 V 10
ns/V
V
CC
@ 5.5 V 8.0
T
A
Operating Ambient Temperature Range −40 25 85 °C
I
OH
Output Current − High −24 mA
I
OL
Output Current − Low 24 mA
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
1. 1. V
in
from 30% to 70% V
CC
; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. 2. V
in
from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.

MC74AC257DR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Encoders, Decoders, Multiplexers & Demultiplexers 2-6V Quad 2-Input Mux w/3-State Out
Lifecycle:
New from this manufacturer.
Delivery:
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