MAX522ESA Datasheet MAX522CSA+T, MAX522ESA+T, MAX522ESA | P7-P9

MAX522

Dual, 8-Bit, Voltage-Output

Serial DAC in 8-Pin SO Package

_______________________________________________________________________________________ 7

_______________Detailed Description

Analog Section

The MAX522 contains two 8-bit, voltage-output digital-

to-analog converters (DACs). The DACs are “inverted”

R-2R ladder networks using complementary switches

that convert 8-bit digital inputs into equivalent analog

output voltages in proportion to the applied reference

voltage.

The MAX522 has one reference input which is shared

by DAC A and DAC B. The device includes output

buffer amplifiers for both DACs and input logic for sim-

ple microprocessor (µP) and CMOS interfaces. The

power-supply range is from +5.5V down to +2.7V.

Reference Input and DAC Output Range

The voltage at REF sets the full-scale output of the

DACs. The input impedance of the REF input is code

dependent. The lowest value, approximately 8kΩ,

occurs when the input code is 01010101 (55hex). The

maximum value of infinity occurs when the input code

is zero.

In shutdown mode, the selected DAC output is set to

zero while the value stored in the DAC register remains

unchanged. This removes the load from the reference

input to save power. Bringing the MAX522 out of shut-

down mode restores the DAC output voltage. Because

the input resistance at REF is code dependent, the

DAC’s reference sources should have an output

impedance of no more than 5Ω. The input capacitance

at the REF pin is also code dependent and typically

does not exceed 25pF.

The reference voltage on REF can range anywhere from

GND to V

. See the

Output Buffer Amplifier

section for

more information.

Output Buffer Amplifiers

DAC A and DAC B voltage outputs are internally

buffered. The buffer amplifiers have a rail-to-rail

(GND to V

) output voltage range.

The DAC outputs are internally divided by two and the

buffer is set to a gain of two, eliminating the need for a

buffer input voltage range to the positive supply rail.

DAC A’s output amplifier can source and sink up to

5mA of current (0.5mA for DAC B’s buffer). See the

Total Unadjusted Error vs. Digital Code graph in the

Typical Operating Characteristics

. The amplifier is

unity-gain stable with a capacitive load of 0.1µF

(0.01µF for DAC B’s buffer) or greater. The slew rate is

limited by the load capacitor and is typically 0.1V/µs

with a 0.1µF load (0.01µF for DAC B’s buffer).

Shutdown Mode

When programmed to shutdown mode, the outputs of

DAC A and DAC B go into a high-impedance state.

Virtually no current flows into or out of the buffer ampli-

fiers in that state. In shutdown mode, the REF inputs

are high impedance (2MΩ typical) to conserve current

drain from the system reference; therefore, the system

reference does not have to be powered down.

Coming out of shutdown, the DAC outputs return to the

values kept in the registers. The recovery time is equiv-

alent to the DAC settling time.

______________________________________________________________Pin Description

NAME FUNCTION

–

—

–

Chip Select (active low). Enables data to be shifted into the 16-bit shift register. Programming commands

are executed at the rising edge of

–

—

–

2 SCLK Serial Clock Input. Data is clocked in on the rising edge of SCLK.

3 V

Positive Power Supply (2.7V to 5.5V). Bypass with 0.22µF to GND.

4 GND Ground

8 DIN Serial Data Input of the 16-bit shift register. Data is clocked into the register on the rising edge of SCLK.

7 REF Reference Input for DAC A and DAC B

6 OUTB

DAC B Output Voltage (Buffered). Connect 0.01µF capacitor or greater to GND.

5 OUTA

DAC A Output Voltage (Buffered). Connect 0.1µF capacitor or greater to GND.

MAX522

Dual, 8-Bit, Voltage-Output

Serial DAC in 8-Pin SO Package

8 _______________________________________________________________________________________

Figure 1. DAC Simplified Circuit Diagram

2R 2R 2R 2R 2R

RRR

REF

GND

OUT

SHOWN FOR ALL 1s ON DAC

Table 1. Input Shift Register

**Clocked in last.

**Clocked in first.

Uncommitted Bit 1

UB1**

Uncommitted Bit 2UB2

Uncommitted Bit 3UB3

Shut Down DAC B, Active HighSB

Shut Down DAC A, Active HighSA

Uncommitted Bit 4UB4

Load Reg DAC B, Active HighLB

Load Reg DAC A, Active HighLA

DAC Data Bit 7 (MSB)B7

DAC Data Bit 6B6

DAC Data Bit 5B5

DAC Data Bit 4B4

DAC Data Bit 3B3

DAC Data Bit 2B2

DAC Data Bit 1B1

DAC Data Bit 0 (LSB)B0*

DATA BITSCONTROL BITS

Serial Interface

An active-low chip select (

–

—

–

) enables the shift register

to receive data from the serial data input. Data is

clocked into the shift register on every rising edge of

the serial clock signal (SCLK). The clock frequency can

be as high as 5MHz.

Data is sent MSB first and can be transmitted in one 16-

bit word. The write cycle can be segmented when

–

—

–

kept active (low) to allow, for example, two 8-bit-wide

transfers. After clocking all 16 bits into the input shift

–

—

–

updates the DAC outputs

and the shutdown status. Because of their single

buffered structure, DACs cannot be simultaneously

updated to different digital values.

Serial-Input Data Format and Control Codes

Table 2 lists the serial-input data format. The 16-bit

input word consists of an 8-bit control byte and an 8-bit

data byte. The 8-bit control byte is not decoded inter-

nally. Every control bit performs one function. Data is

clocked in starting with UB1 (Uncommitted Bit), fol-

lowed by the remaining control bits and the data byte.

The LSB of the data byte (B0) is the last bit clocked into

the shift register (Figure 2).

Table 3 is an example of a 16-bit input word. It per-

forms the following functions:

• 80hex (128 decimal) loaded into DAC registers

A and B.

• DAC A and DAC B are active.

MAX522

Dual, 8-Bit, Voltage-Output

Serial DAC in 8-Pin SO Package

_______________________________________________________________________________________ 9

DIN

SCLK

UB1 UB2 UB3 SB SA UB4 LB LA D7 D6 D5 D4 D3 D2 D1 D0

OPTIONAL

INSTRUCTION

EXECUTED

(CONTROL BYTE) (DATA BYTE)

Figure 2. MAX522 3-Wire Serial-Interface Timing Diagram

Table 2. Serial-Interface Programming Commands

Table 3. Example of a 16-Bit Input Word

X =

Don’t care.

* = Not shown, for the sake of clarity. The functions of loading and shutting down the DACs and programming the logic can be combined in a single

command.

X X 1 0 0 0 1 1 1 0 0 0 0 0 0 0

UB1 UB2 UB3 SB SA UB4 LB LA B7 B6 B5 B4 B3 B2 B1 B0

Loaded Loaded

in First in Last

CONTROL

1 * 0XX 1

X 0

0 0

B6 B5

Shut Down All DACsXXXXXXXX**0111XX

Shut Down DAC AXXXXXXXX**0101XX

Shut Down DAC BXXXXXXXX**0011XX

Unassigned CommandXXXXXXXX**0001XX

All DACs ActiveX

XXXXXX

X**0001XX

Load Both DAC Registers8-Bit DAC Data*

Load Register to DAC A8-Bit DAC Data*

Load Register to DAC B8-Bit DAC Data*

Unassigned Command*

No Operation to DAC RegistersX

XXXXXXX

000*

1XX

FUNCTION

LSB

B1B2B3B4

MSB

LALBUB4SASBUB3UB2

UB1

DATA

P1-P3 P4-P6 P7-P9 P10-P12

MAX522ESA

Mfr. #:

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Maxim Integrated

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Digital to Analog Converters - DAC Dual, 8-Bit, Voltage-Output Serial DAC in 8-Pin SO Package

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MAX522ESA

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