REV. A
AD7675
–10–
IN+
REF
REFGND
IN–
32,768C 16,384C
MSB
4C 2C C C
LSB
SW
+
SWITCHES
CONTROL
32,768C 16,384C
MSB
4C 2C C C
LSB
SW
–
BUSY
OUTPUT
CODE
CNVST
CONTROL
LOGIC
COMP
Figure 3. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7675 is a fast, low power, single-supply, precise 16-bit
analog-to-digital converter (ADC). The AD7675 is capable of
converting 100,000 samples per second (100 kSPS) and allows
power saving between conversions. When operating at 100 SPS,
for example, it consumes typically only 15 µW. This feature
makes the AD7675 ideal for battery-powered applications.
The AD7675 provides the user with an on-chip track/hold,
successive approximation ADC that does not exhibit any pipe-
line or latency, making it ideal for multiple multiplexed channel
applications.
The AD7675 can be operated from a single 5 V supply and be
interfaced to either 5 V or 3 V digital logic. It is housed in a
48-lead LQFP package that combines space savings and allows
flexible configurations as either serial or parallel interface. The
AD7675 is pin-to-pin compatible with the AD7660.
CONVERTER OPERATION
The AD7675 is a successive approximation analog-to-digital
converter based on a charge redistribution DAC. Figure 3 shows
the simplified schematic of the ADC. The capacitive DAC con-
sists of two identical arrays of 16 binary-weighted capacitors that
are connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to AGND via SW
+
and SW
–
.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire both analog signals.
When the acquisition phase is complete and the CNVST input
goes or is low, a conversion phase is initiated. When the con-
version phase begins, SW
+
and SW
–
are opened first. The two
capacitor arrays are then disconnected from the inputs and
connected to the REFGND input. Therefore, the differential
voltage between the output of IN+ and IN– captured at the
end of the acquisition phase is applied to the comparator inputs,
causing the comparator to become unbalanced.
By switching each element of the capacitor array between
REFGND or REF, the comparator input varies by binary
weighted voltage steps (V
REF
/2, V
REF
/4 . . .V
REF
/65536). The
control logic toggles these switches, starting with the MSB first,
in order to bring the comparator back into a balanced condition.
After the completion of this process, the control logic generates
the ADC output code and brings BUSY output low.
Transfer Functions
Using the OB/2C digital input, the AD7675 offers two output
codings: straight binary and two’s complement. The ideal trans-
fer characteristic for the AD7675 is shown in Figure 4.
000...000
000...001
000...010
111...101
111...110
111...111
ANALOG INPUT
+FS – 1.5 LSB
+FS – 1 LSB
–FS + 1 LSB–FS
–FS + 0.5 LSB
ADC CODE – Straight Binary
Figure 4. ADC Ideal Transfer Function
TEMPERATURE – C
5
3
–5
–55 135–35
LSB
–15 –5 15 35 55 75 95
1
–1
–3
115
4
2
0
–2
–4
–FS
OFFSET
+FS
TPC 13. Drift vs. Temperature
