© Semiconductor Components Industries, LLC, 2012
June, 2012 Rev. 6
1 Publication Order Number:
NB7L14M/D
NB7L14M
2.5V/3.3V Differential 1:4
Clock/Data Fanout Buffer/
Translator with CML
Outputs and Internal
Termination
Description
The NB7L14M is a differential 1to4 clock/data distribution chip
with internal source terminated CML output structures, optimized for
minimal skew and jitter. Device produces four identical output copies
of clock or data operating up to 8 GHz or 12 Gb/s, respectively. As
such, NB7L14M is ideal for SONET, GigE, Fiber Channel, Backplane
and other clock/data distribution applications.
Inputs incorporate internal 50 W termination resistors and accept
LVPECL, CML, LVCMOS, LVTTL, or LVDS (See Table 6).
Differential 16 mA CML outputs provide matching internal 50 W
terminations, and 400 mV output swings when externally terminated
with 50 W to V
CC
(See Figure 14).
The device is offered in a low profile 3x3 mm 16pin QFN package.
Application notes, models, and support documentation are available at
www.onsemi.com.
Features
Maximum Input Clock Frequency up to 8 GHz Typical
Maximum Input Data Rate up to 12 Gb/s Typical
< 0.5 ps of RMS Clock Jitter
< 10 ps of Data Dependent Jitter
30 ps Typical Rise and Fall Times
110 ps Typical Propagation Delay
6 ps Typical Within Device Skew
Operating Range: V
CC
= 2.375 V to 3.465 V with V
EE
= 0 V
CML Output Level (400 mV PeaktoPeak Output) Differential
Output Only
50 W Internal Input and Output Termination Resistors
Functionally Compatible with Existing 2.5 V/3.3 V LVEL, LVEP, EP
and SG Devices
These are PbFree Devices
Figure 1. Logic Diagram
50 W
50 W
V
TCLK
CLK
CLK
V
TCLK
Q3
Q3
Q2
Q2
Q1
Q1
Q0
Q0
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAM*
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
QFN16
MN SUFFIX
CASE 485G
16
NB7L
14M
ALYWG
G
1
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
(Note: Microdot may be in either location)
1
NB7L14M
http://onsemi.com
2
V
EE
Q3 Q3 V
CC
V
EE
Q0 Q0 V
CC
Q1
Q1
Q2
Q2
V
TCLK
CLK
CLK
V
TCLK
5678
16 15 14 13
12
11
10
9
1
2
3
4
NB7L14M
Exposed Pad (EP)
Figure 2. QFN16 Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin Name I/O Description
1 V
TCLK
Internal 50 W Termination Pin for CLK.
2 CLK LVPECL, CML,
LVCMOS, LVTTL,
LVDS
Inverted Differential Clock/Data Input. (Note 1)
3 CLK LVPECL, CML,
LVCMOS, LVTTL,
LVDS
Noninverted Differential Clock/Data Input. (Note 1)
4 V
TCLK
Internal 50 W Termination Pin for CLK.
5,16 V
EE
Power Supply Negative Supply Voltage. All V
EE
pins must be externally connected to a Power Supply to
guarantee proper operation.
6 Q3 CML Output
Inverted Differential Output 3 with Internal 50 W Source Termination Resistor. (Note 2)
7 Q3 CML Output
Noninverted Differential Output 3 with Internal 50 W Source Termination Resistor. (Note 2)
8,13 V
CC
Power Supply Positive Supply Voltage. All V
CC
pins must be externally connected to a Power Supply to
guarantee proper operation.
9 Q2 CML Output
Inverted Differential Output 2 with Internal 50 W Source Termination Resistor. (Note 2)
10 Q2 CML Output
Noninverted Differential Output 2 with Internal 50 W Source Termination Resistor. (Note 2)
11 Q1 CML Output
Inverted Differential Output 1 with Internal 50 W Source Termination Resistor. (Note 2)
12 Q1 CML Output
Noninverted Differential Output 1 with Internal 50 W Source Termination Resistor. (Note 2)
14 Q0 CML Output
Inverted Differential Output 0 with Internal 50 W Source Termination Resistor. (Note 2)
15 Q0 CML Output
Noninverted Differential Output 0 with Internal 50 W Source Termination Resistor. (Note 2)
EP Exposed Pad. Thermal pad on the package bottom must be attached to a heatsinking
conduit to improve heat transfer. It is recommended to connect the EP to the lower
potential (V
EE
).
1. In the differential configuration when the input termination pins (V
TCLK
, V
TCLK
) are connected to a common termination voltage or left open,
and if no signal is applied on CLK and CLK
, then the device will be susceptible to selfoscillation.
2. CML outputs require 50 W receiver termination resistors to V
CC
for proper operation.
NB7L14M
http://onsemi.com
3
Table 2. ATTRIBUTES
Characteristics Value
ESD Protection Human Body Model
Machine Model
Charged Device Model
> 1500 V
> 50 V
> 500 V
Moisture Sensitivity (Note 3) Pb Pkg PbFree Pkg
QFN16 Level 1 Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 @ 0.125 in
Transistor Count 387
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Units
V
CC
Positive Power Supply V
EE
= 0 V 3.6 V
V
I
Input Voltage V
EE
= 0 V V
EE
v V
I
v V
CC
3.6 V
V
INPP
Differential Input Voltage |CLK CLK| V
CC
V
EE
w 2.8 V
V
CC
V
EE
< 2.8 V
2.8
|V
CC
V
EE
|
V
V
I
IN
Input Current Through R
T
(50 W Resistor)
Static
Surge
45
80
mA
mA
I
out
Output Current Continuous
Surge
25
50
mA
mA
T
A
Operating Temperature Range QFN16 40 to +85 °C
T
stg
Storage Temperature Range 65 to +150 °C
q
JA
Thermal Resistance (JunctiontoAmbient)
(Note 4)
0 lfpm
500 lfpm
QFN16
QFN16
42
36
°C/W
°C/W
q
JC
Thermal Resistance (JunctiontoCase) 2S2P (Note 4) QFN16 3 to 4 °C/W
T
sol
Wave Solder Pb
PbFree
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
4. JEDEC standard multilayer board 2S2P (2 signal, 2 power).

NB7L14MMNR2

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 2.5V/3.3V Multilevel
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet