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NB3N201SDR2G
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P19
NB3N201S, NB3N206S
www
.onsemi.com
10
A. All input pulses are supplied by an Agilent 8304A Stimulus System.
B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software
C. Period jitter is measured using a 100 MHz 50
±
1% duty cycle clock input.
D. Peak−to−peak jitter is measured using a 200 Mbps 2
15
−1 PRBS input.
Figure 10. Driver Jitter Measurement W
aveforms
Figure 1
1. Receiver V
oltage and Current Definitions
NB3N201S, NB3N206S
www
.onsemi.com
11
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤
1 ns, frequency = 50 MHz, duty cycle = 50
±
5%. C
L
is a combination of a 20%−tolerance, low−loss ceramic, surface−mount capacitor and fixture capacitance within 2 cm of the
D.U.T
.
B. The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz.
Figure 12. Receiver Timing T
est Circuit and Waveforms
NB3N201S, NB3N206S
www
.onsemi.com
12
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤
1 ns, frequency = 500 kHz, duty cycle = 50
±
5%.
B. R
L
is 1% tolerance, metal film, surface mount, and located within 2 cm of the D.U.T
.
C. C
L
is the instrumentation and fixture capacitance within 2 cm of the DUT and 20%.
Figure 13. Receiver Enable/Disable Time T
est Circuit and Waveforms
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P19
NB3N201SDR2G
Mfr. #:
Buy NB3N201SDR2G
Manufacturer:
ON Semiconductor
Description:
Clock Buffer M-LVDS DRIVER RECEIVER
Lifecycle:
New from this manufacturer.
Delivery:
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Ups
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EMS
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Products related to this Datasheet
NB3N201SDG
NB3N206SDG
NB3N206SDR2G
NB3N201SDR2G