74AUP2G79 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 8 — 24 January 2013 12 of 25
NXP Semiconductors
74AUP2G79
Low-power dual D-type flip-flop; positive-edge trigger
[1] All typical values are measured at nominal V
CC
.
[2] t
pd
is the same as t
PLH
and t
PHL
.
[3] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
V
CC
2
f
i
N+(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC
2
f
o
) = sum of the outputs.
12. Waveforms
C
PD
power
dissipation
capacitance
f = 1 MHz;
V
I
=GNDtoV
CC
[3]
V
CC
= 0.8 V - 1.6 - - - - - pF
V
CC
= 1.1 V to 1.3 V - 1.7 - - - - - pF
V
CC
= 1.4 V to 1.6 V - 1.8 - - - - - pF
V
CC
= 1.65 V to 1.95 V - 1.9 - - - - - pF
V
CC
= 2.3 V to 2.7 V - 2.3 - - - - - pF
V
CC
= 3.0 V to 3.6 V - 2.7 - - - - - pF
Table 8. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max Min Max
Measurement points are given in Table 9.
Logic levels: V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 8. The clock input (nCP) to output (nQ) propagation delays
001aaf271
nCP input
nQ output
t
PHL
t
PLH
V
M
V
M
V
OH
V
I
GND
nD input
V
I
GND
V
OL
V
M
V
M
