4
ICS91309
0093H—12/09/08
Electrical Characteristics - Outputs
T
A
= 0 - 70°C; V
DD
= 3.3 V +/-10%; C
L
= 30 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output High Voltage
V
OH
I
OH
= -12 mA
2.4 V
Output Low Voltage
V
OL
I
OL
= 12 mA
0.4 V
Rise Time
1
t
r
Measure between 0.8 V and 2.0 V 1.2 1.5 ns
Fall Time
1
t
f
Measure between 2.0 V and 0.8 V 1.2 1.5 ns
PLL Lock Time
1
T
LOCK
Stable V
DD
, valid clock on REF
1mS
f
1
C
L
= 30 pF
10 100 MHz
f
1
C
L
= 10 pF
10 133 MHz
Dt1
Measured at 1.4 V, Fout = 66.7 MHz 40
50 60 %
Dt2
Measured at V
DD
/2, Fout < 50.0 MHz
45 50 55 %
Jitter, C
y
cle-to-c
y
cle
1
t
j
c
y
c-c
y
c
Measured at 66.7 MHz, loaded outputs 125 ps
Jitter, Absolute
1
Tjabs
10,000 cycles, C
L
= 30 pF
-100 70 100 ps
Jitter, 1-Si
g
ma
1
Tj1s
10,000 cycles, C
L
= 30 pF
14 30 ps
Skew, Grou
p
-to-Grou
p
1
Tsk Measured at 1.4 V 215 ps
Skew, Out
p
ut-to-Out
p
ut
1
Tsk Measured at 1.4 V, within a group 100 ps
Skew, Device-to-Device
1
Tdsk-Tdsk
Measured at V
DD
/2,on CLKOUT pins
700 ps
Dela
, Input-to-Output
1
Dr1 Measured at 1.4 V 700 ps
Notes:
1. Guaranteed by design and characterization, not 100% tested in production.
Duty Cycle
1
Output Frequency
5
ICS91309
0093H—12/09/08
Output to Output Skew
The skew between CLKOUT and the CLKA/B outputs is not dynamically adjusted by the PLL. Since CLKOUT is one
of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded,
zero phase difference will maintained from REF to all outputs.
If applications requiring zero output-output skew, all the outputs must equally loaded.
If the CLKA/B outputs are less loaded than CLKOUT, CLKA/B outputs will lead it; and if the CLKA/B is more loaded
than CLKOUT, CLKA/B will lag the CLKOUT.
Since the CLKOUT and the CLKA/B outputs are identical, they all start at the same time, but different loads cause them
to have different rise times and different times crossing the measurement thresholds.
REF input and
all outputs
loaded
Equally
REF input and CLKA/B
outputs loaded equally, with
CLKOUT loaded More.
REF input and CLKA/B
outputs loaded equally, with
CLKOUT loaded Less.
Timing diagrams with different loading configurations
6
ICS91309
0093H—12/09/08
Application Suggestion:
ICS91309 is a mixed analog/digital product. The analog portion of the PLL is very sensitive to any random noise
generated by charging or discharging of internal or external capacitor on the power supply pins. This type of noise will
cause excess jitter to the outputs of ICS91309. Below is a recommended lay out to alleviate any addition noise. For
additional information on FT. layout, please refer to our AN07. The 0.1 uF capacitors should be connected as close as
possible to power pins (4 & 13). An Isolated power plane with a 2.2 uF capacitor to ground will enhance the power line
stability.
33
33
33
33
10K
0.1µF
VDD
GND
33
33
33
33
33
10K
0.1µF
VDD
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
REF
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
FS2
CLKOUT
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
FS1

91309AGILFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer Low SKEW BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
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