ADT7461A
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13
transmitted over the serial bus in a single read or
write operation is limited only by what the master
and slave devices can handle.
3. When all data bytes have been read or written,
stop conditions are established. In write mode, the
master pulls the data line high during the tenth
clock pulse to assert a stop condition. In read
mode, the master device overrides the
acknowledge bit by pulling the data line high
during the low period before the ninth clock pulse.
This is known as no acknowledge. The master
takes the data line low during the low period
before the tenth clock pulse, then high during the
tenth clock pulse to assert a stop condition.
Any number of bytes of data are transferable over
the serial bus in one operation, but it is not
possible to mix read and write in one operation
because the type of operation is determined at the
beginning and cannot subsequently be changed
without starting a new operation. For the
ADT7461A, write operations contain either one or
two bytes, while read operations contain one byte.
To write data to one of the device data registers, or to read
data from it, the address pointer register must be set so that
the correct data register is addressed. The first byte of a write
operation always contains a valid address that is stored in the
address pointer register. If data is to be written to the device,
the write operation contains a second data byte that is written
to the register selected by the address pointer register.
This procedure is illustrated in Figure 15. The device
address is sent over the bus followed by R/W
set to 0. This
is followed by two data bytes. The first data byte is the
address of the internal data register to be written to, which
is stored in the address pointer register. The second data byte
is the data to be written to the internal data register.
Figure 15. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
Figure 16. Writing to the Address Pointer Register Only
Figure 17. Reading from a Previously Selected Register
D7 D6 D5 D4 D3 D2 D1 D0
FRAME 3
DATA BYTE
ACK. BY
ADT7461A
STOP BY
MASTER
SDATA (CONTINUED)
SCLK (CONTINUED)
FRAME 1
SERIAL BUS ADDRESS BYTE
ACK. BY
ADT7461A
SDATA
SCLK
START BY
MASTER
FRAME 2
ADDRESS POINTER REGISTER BYTE
D7 D6 D5 D4 D3 D2 D1 D0A6 A5 A4 A3 A2 A1 A0 R/W
ACK. BY
ADT7461A
1 19 9
1
9
FRAME 1
SERIAL BUS ADDRESS BYTE
ACK. BY
ADT7461A
SDATA
SCLK
START BY
MASTER
FRAME 2
ADDRESS POINTER REGISTER BYTE
D7 D6 D5 D4 D3 D2 D1 D0A6 A5 A4 A3 A2 A1 A0 R/W
ACK. BY
ADT7461A
1 19 9
STOP BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
ACK. BY
ADT7461A
SDATA
SCLK
START BY
MASTER
FRAME 2
ADDRESS POINTER REGISTER BYTE
D7 D6 D5 D4 D3 D2 D1 D0A6 A5 A4 A3 A2 A1 A0 R/W
ACK. BY
ADT7461A
1 19 9
STOP BY
MASTER
ADT7461A
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14
When reading data from a register there are two
possibilities.
If the address pointer register value of the ADT7461A
is unknown or not the desired value, it is first necessary
to set it to the correct value before data can be read
from the desired data register. This is done by writing
to the ADT7461A as before, but only the data byte
containing the register read address is sent, because
data is not to be written to the register see Figure 16.
A read operation is then performed consisting of the
serial bus address, R/W
bit set to 1, followed by the
data byte read from the data register see Figure 17.
If the address pointer register is known to be at the
desired address, data can be read from the
corresponding data register without first writing to the
address pointer register and the bus transaction shown
in Figure 16 can be omitted.
Notes:
It is possible to read a data byte from a data register
without first writing to the address pointer register.
However, if the address pointer register is already at the
correct value, it is not possible to write data to a register
without writing to the address pointer register because
the first data byte of a write is always written to the
address pointer register.
Some of the registers have different addresses for read
and write operations. The write address of a register
must be written to the address pointer if data is to be
written to that register, but it may not be possible to
read data from that address. The read address of a
register must be written to the address pointer before
data can be read from that register.
ALERT Output
This is applicable when Pin 6 is configured as an ALERT
output. The ALERT output goes low whenever an
outoflimit measurement is detected, or if the remote
temperature sensor is open circuit. It is an opendrain output
and requires a pullup resistor. Several ALERT
outputs can
be wireOR’ed together, so that the common line goes low
if one or more of the ALERT
outputs goes low.
The ALERT
output can be used as an interrupt signal to a
processor, or as an SMBALERT
. Slave devices on the SMBus
cannot normally signal to the bus master that they want to
talk, but the SMBALERT
function allows them to do so.
One or more ALERT
outputs can be connected to a
common SMBALERT
line that is connected to the master.
When the SMBALERT
line is pulled low by one of the
devices, the following procedure occurs (see Figure 18):
Figure 18. Use of SMBALERT
ALERT RESPONSE
ADDRESS
MASTER SENDS
ARA AND READ
COMMAND
DEVICE SENDS
ITS ADDRESS
RDSTART ACK
DEVICE
ADDRESS
NO
ACK
STOP
MASTER
RECEIVES
SMBALERT
1. SMBALERT is pulled low.
2. Master initiates a read operation and sends the
alert response address (ARA = 0001 100). This is
a general call address that must not be used as a
specific device address.
3. The device whose ALERT
output is low responds
to the alert response address and the master reads
its device address. As the device address is seven
bits, an LSB of 1 is added. The address of the
device is now known and it can be interrogated in
the usual way.
4. If more than one device’s ALERT
output is low,
the one with the lowest device address takes
priority, in accordance with normal SMBus
arbitration.
Once the ADT7461A has responded to the alert response
address, it resets its ALERT
output, provided that the error
condition that caused the ALERT
no longer exists. If the
SMBALERT
line remains low, the master sends the ARA
again, and so on until all devices whose ALERT
outputs
were low have responded.
Low Power Standby Mode
The ADT7461A can be put into low power standby mode
by setting Bit 6 of the configuration register. When Bit 6 is
low, the ADT7461A operates normally. When Bit 6 is high,
the ADC is inhibited, and any conversion in progress is
terminated without writing the result to the corresponding
value register. However, the SMBus is still enabled. Power
consumption in the standby mode is reduced to 5 mA if there
is no SMBus activity, or 30 mA if there are clock and data
signals on the bus.
When the device is in standby mode, it is possible to
initiate a oneshot conversion of both channels by writing to
the oneshot register (Address 0x0F), after which the device
returns to standby. It does not matter what is written to the
oneshot register, all data written to it is ignored. It is also
possible to write new values to the limit register while in
standby mode. If the values stored in the temperature value
registers are outside the new limits, an ALERT
is generated,
even though the ADT7461A is still in standby.
ADT7461A
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15
Sensor Fault Detection
At its D+ input, the ADT7461A contains internal sensor
fault detection circuitry. This circuit can detect situations
where an external remote diode is either not connected or
incorrectly connected to the ADT7461A. A simple voltage
comparator trips if the voltage at D+ exceeds V
DD
1 V
(typical), signifying an open circuit between D+ and D.
The output of this comparator is checked when a conversion
is initiated. Bit 2 of the status register (open flag) is set if a
fault is detected. If the ALERT
pin is enabled, setting this
flag causes ALERT
to assert low.
If the user does not wish to use an external sensor with the
ADT7461A, tie the D+ and D inputs together to prevent
continuous setting of the open flag.
The ADT7461A Interrupt System
The ADT7461A has two interrupt outputs, ALERT and
THERM
. Both have different functions and behavior.
ALERT
is maskable and responds to violations of software
programmed temperature limits or an opencircuit fault on
the external diode. THERM
is intended as a failsafe
interrupt output that cannot be masked.
If the external or local temperature exceeds the
programmed high temperature limits, or equals or exceeds
the low temperature limits, the ALERT
output is asserted
low. An opencircuit fault on the external diode also causes
ALERT
to assert. ALERT is reset when serviced by a master
reading its device address, provided the error condition has
gone away and the status register has been reset.
The THERM
output asserts low if the external or local
temperature exceeds the programmed THERM
limits.
THERM
temperature limits should normally be equal to or
greater than the high temperature limits. THERM
is reset
automatically when the temperature falls back within the
THERM
limit. The external and local limits are set by
default to 85°C. A hysteresis value can be programmed; in
which case, THERM
resets when the temperature falls to the
limit value minus the hysteresis value. This applies to both
local and remote measurement channels. The poweron
hysteresis default value is 10°C, but this can be
reprogrammed to any value after powerup.
The hysteresis loop on the THERM
outputs is useful when
THERM
is used, for example, as an on/off controller for a
fan. The users system can be set up so that when THERM
asserts, a fan is switched on to cool the system. When
THERM
goes high again, the fan can be switched off.
Programming a hysteresis value protects from fan jitter,
where the temperature hovers around the THERM
limit, and
the fan is constantly switched.
Table 10. THERM Hysteresis
THERM Hysteresis Binary Representation
0°C 0 000 0000
1°C 0 000 0001
10°C 0 000 1010
Figure 19 shows how the THERM and ALERT outputs
operate. The ALERT
output can be used as a SMBALERT
to signal to the host via the SMBus that the temperature has
risen. The user can use the THERM
output to turn on a fan
to cool the system, if the temperature continues to increase.
This method ensures that there is a failsafe mechanism to
cool the system, without the need for host intervention.
Figure 19. Operation of the ALERT and THERM
Interru
p
ts
1
32
4
HIGH TEMP LIMIT
RESET BY MASTER
ALERT
THERM
1005C
TEMPERATURE
905C
805C
705C
605C
505C
405C
THERM LIMIT
THERM LIMITHYSTERESI
S
If the measured temperature exceeds the high
temperature limit, the ALERT
output asserts low.
If the temperature continues to increase and exceeds the
THERM
limit, the THERM output asserts low. This can
be used to throttle the CPU clock or switch on a fan.
The THERM output deasserts (goes high) when the
temperature falls to THERM
limit minus hysteresis. In ,
the default hysteresis value of 10°C is shown.
The ALERT output deasserts only when the
temperature has fallen below the high temperature
limit, and the master has read the device address and
cleared the status register.
Pin 6 on the ADT7461A can be configured as either an
ALERT
output or as an additional THERM output.
THERM2 asserts low when the temperature exceeds the
programmed local and/or remote high temperature
limits. It is reset in the same manner as THERM and is
not maskable.
The programmed hysteresis value also applies to
THERM2
.
Figure 20 shows how THERM
and THERM2 operate
together to implement two methods of cooling the system.
In this example, the THERM2
limits are set lower than the
THERM
limits. The THERM2 output is used to turn on a
fan. If the temperature continues to rise and exceeds the
THERM
limits, the THERM output provides additional
cooling by throttling the CPU.

ADT7461AARMZ-2REEL

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
SENSOR DIGITAL -40C-120C MICRO8
Lifecycle:
New from this manufacturer.
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