W232ZXC-10 Datasheet W232ZXC-10 | P1-P3

W232

Ten Output Zero Delay Buffer

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-07167 Rev. *E Revised April 27, 2009

Features

■ Well-Suited to both 100 and 133 MHz Designs

■ 10 or 11 LVCMOS/LVTTL Outputs

■ 3.3V Power Supply

■ Available in 24-Pin TSSOP Package

Key Specifications

■ Operating Voltage: 3.3V ± 10%

■ Operating Range: 25 MHz < f

OUT

< 140 MHz

■ Cycle-to-Cycle Jitter less than 150 ps

■ Output to Output Skew less than100 ps

■ Phase Error Jitter less than 125 ps

■ Static Phase Error: less than 150 ps

Pinouts

Figure 1. 24-Pin TSSOP - W232-09 Figure 2. 24-Pin TSSOP - W232-10

PLL

OE0:4

FBOUT

OE5:8

Configuration of these blocks dependent upon specific option being used.

FBIN

CLK

Logic Block Diagram

CLK

AVDD

VDD

GND

VDD

OE5:8

FBIN

AGND

VDD

GND

VDD

OE0:4

FBOUT

W232-09

CLK

AVDD

VDD

GND

VDD

FBIN

AGND

VDD

GND

VDD

FBOUT

W232-10

[+] Feedback

W232

Document #: 38-07167 Rev. *E Page 2 of 6

Overview

The W232 is a PLL-based clock driver designed for use in systems requiring a large number of synchronous timing signals. The clock

driver has output frequencies of up to 140 MHz and output-to-output skews of less than 100 ps. The W232 provides minimum

cycle-to-cycle and long-term jitter, which is of significant importance to meet the tight input-to-input skew budget in DIMM applications.

The W232 was specifically designed to accept SSFTG signals currently being used in motherboard designs to reduce EMI. Zero delay

buffers which are not designed to pass this feature through may cause skewing failures.

Output enable pins allow shutdown of output when they are not being used. This reduces EMI and power consumption.

Pin Definitions

Pin Name

Pin No.

(-09)

Pin No.

(-10)

Pin Type Pin Description

CLK 24 24 I Reference Input: Output signals Q0:9 are synchronized to this signal.

FBIN 13 13 I Feedback Input: This input must be fed by one of the outputs (typically FBOUT)

to ensure proper functionality. If the trace between FBIN and FBOUT is equal

in length to the traces between the outputs and the signal destinations, then the

signals received at the destinations are synchronized to the CLK signal input.

Q0:8 3, 4, 5, 8, 9,

16, 17, 20, 21

3, 4, 5, 8, 9, 15,

16, 17, 20, 21

O Outputs: The frequency and phase of the signals provided by these pins are

equal to the reference signal if properly laid out.

FBOUT 12 12 O Feedback Output: Typically this is connected directly to the FBIN input with a

trace equal in length to the traces between outputs Q0:9 and the destination

points of these output signals.

AVDD 23 23 P Analog Power Connection: Connect to 3.3V. Use ferrite beads to help reduce

noise for optimal jitter performance.

AGND 1 1 G Analog Ground Connection: Connect to common system ground plane.

VDD 2, 10, 15, 22 2, 10, 14 22 P Power Connections: Connect to 3.3V. Use ferrite beads to help reduce noise

for optimal jitter performance.

GND 6, 7, 18, 19 6, 7, 18, 19 G Ground Connections: Connect to common system ground plane.

OE0:4 11 – I Output Enable Input: Tie to V

(HIGH, 1) for normal operation. When brought

to GND (LOW, 0) outputs Q0:4 are disabled to a LOW state.

OE – 11 I Output Enable Input: Tie to V

(HIGH, 1) for normal operation. When brought

to GND (LOW, 0) outputs Q0:9 are disabled to a LOW state.

OE5:8 14 – I Output Enable Input: Tie to V

(HIGH, 1) for normal operation. When brought

to GND (LOW, 0) outputs Q5:8 are disabled to a LOW state.

[+] Feedback

W232

Document #: 38-07167 Rev. *E Page 3 of 6

Figure 3. Schematic

Spread Aware

Many systems being designed now use a technology called

Spread Spectrum Frequency Timing Generation (SSFTG).

Cypress has been one of the pioneers of SSFTG development,

and designed this product so as not to filter off the Spread

Spectrum (SS) feature of the Reference input, assuming it exists.

When a zero delay buffer is not designed to pass the SS feature

through, the result is a significant amount of tracking skew which

may cause problems in systems requiring synchronization.

For more details on SS timing technology, see the Cypress appli-

cation note titled, “EMI Suppression Techniques with Spread

Spectrum Frequency Timing Generator (SSFTG) ICs” - AN1278.

How to Implement Zero Delay

Typically, Zero Delay Buffers (ZDBs) are used because a

designer wants to provide multiple copies of a clock signal in

phase with each other. The whole concept behind ZDBs is that

the signals at the destination chips are all going HIGH at the

same time as the input to the ZDB. To achieve this, layout must

compensate for trace length between the ZDB and the target

devices. The method of compensation is as follows.

External feedback is the trait that allows this compensation.

Since the PLL on the ZDB causes the feedback signal to be in

phase with the reference signal, when laying out the board,

match the trace lengths between the output being used for

feedback and the FBIN input to the PLL.

If it is desirable to either add a little delay, or slightly precede the

input signal, this may also be affected by either making the trace

to the FBIN pin a little shorter or a little longer than the traces to

the devices being clocked.

Inserting Other Devices in Feedback Path

Another nice feature available due to the external feedback is the

ability to synchronize signals up to the signal coming from some

other device. This implementation can be applied to any device

(ASIC, multiple output clock buffer/driver, and so on) which is put

into the feedback path.

As shown in Figure 4, if the traces between the ASIC/buffer and

the destination of the clock signal(s) (A) are equal in length to the

trace between the buffer and the FBIN pin, the signals at the

destination(s) device are driven HIGH at the same time the

Reference clock provided to the ZDB goes HIGH. Synchronizing

the other outputs of the ZDB to the outputs form the ASIC/Buffer

is, however, more complex as any propagation delay in the

ASIC/Buffer must be accounted for.

Figure 4. 6 Output Buffer in the Feedback Path

GND

AGND

FBIN

VDD

AVDD

GND

FBOUT

VDD

0.1

VDD

0.1

VDD

0.1

3.3V

0.1

W232-10

Reference

Signal

Feedback

Input

ASIC/

Buffer

Zero

Delay

Buffer

[+] Feedback

P1-P3 P4-P6

W232ZXC-10

Mfr. #:

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Manufacturer:

Cypress Semiconductor

Description:

Phase Locked Loops - PLL Spread Aware Zero Delay Buffer

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W232ZXC-10