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DM74LS73AN

P1-P3P4-P5
© 2000 Fairchild Semiconductor Corporation DS006372 www.fairchildsemi.com
August 1986
Revised March 2000
DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
DM74LS73A
Dual Negative-Edge-Triggered Master-Slave
J-K Flip-Flops with Clear and Complementary Outputs
General Description
This device contains two independent negative-edge-trig-
gered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flops on the falling edge of
the clock pulse. The clock triggering occurs at a voltage
level and is not directly related to the transition time of the
negative going edge of the clock pulse. The data on the J
and K inputs is allowed to change while the clock is HIGH
or LOW without affecting the outputs as long as setup and
hold times are not violated. A low logic level on the clear
input will reset the outputs regardless of the levels of the
other inputs.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram Function Table
H = HIGH Logic Level
L = LOW Logic Level
X = Either LOW or HIGH Logic Level
↓ = Negative going edge of pulse.
Q
0
= The output logic level before the indicated input conditions were
established.
Toggle = Each output changes to the complement of its previous level on
each falling edge of the clock pulse.
Order Number Package Number Package Description
DM74LS73AM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS73AN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs Outputs
CLR CLK J K Q Q
LXXXL H
H ↓ LL Q
0
Q
0
H ↓ HL H L
H ↓ LH L H
H ↓ H H Toggle
HHXXQ
0
Q
0
www.fairchildsemi.com 2
DM74LS73A
Absolute Maximum Ratings(Note 1)
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Note 2: C
L
= 15 pF, R
L
= 2 kΩ, T
A
= 25°C and V
CC
= 5V.
Note 3: C
L
= 50 pF, R
L
= 2 kΩ, T
A
= 25°C and V
CC
= 5V.
Note 4: The symbol (↓) indicates the falling edge of the clock pulse is used for reference.
Supply Voltage 7V
Input Voltage 7V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range −65°C to +150°C
Symbol Parameter Min Nom Max Units
V
CC
Supply Voltage 4.75 5 5.25 V
V
IH
HIGH Level Input Voltage 2 V
V
IL
LOW Level Input Voltage 0.8 V
I
OH
HIGH Level Output Current −0.4 mA
I
OL
LOW Level Output Current 8 mA
f
CLK
Clock Frequency (Note 2) 0 30 MHz
f
CLK
Clock Frequency (Note 3) 0 25 MHz
t
W
Pulse Width Clock HIGH 20
(Note 2) Preset LOW 25 ns
Clear LOW 25
t
W
Pulse Width Clock HIGH 25
(Note 3) Preset LOW 30 ns
Clear LOW 30
t
SU
Setup Time (Note 2)(Note 4) 20↓ ns
t
SU
Setup Time (Note 3)(Note 4) 25↓ ns
t
H
Hold Time (Note 2)(Note 4) 0↓ ns
t
H
Hold Time (Note 3)(Note 4) 5↓ ns
T
A
Free Air Operating Temperature 0 70 °C
3 www.fairchildsemi.com
DM74LS73A
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Note 5: All typicals are at V
CC
= 5V, T
A
= 25°C.
Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedback from the outputs,
where shorting the outputs to ground may cause the outputs to change logic state, an equivalent test may be performed where V
O
= 2.125V with the mini-
mum and maximum limits reduced by one half from their stated values. This is very useful when using automatic test equipment.
Note 7: With all outputs OPEN, I
CC
is measured with the Q and Q outputs HIGH in turn. At the time of measurement, the clock is grounded.
Switching Characteristics
at V
CC
= 5V and T
A
= 25°C
Symbol Parameter Conditions Min
Typ
Max Units
(Note 5)
V
I
Input Clamp Voltage V
CC
= Min, I
I
= −18 mA −1.5 V
V
OH
HIGH Level V
CC
= Min, I
OH
= Max
2.7 3.4 V
Output Voltage V
IL
= Max, V
IH
= Min
V
OL
LOW Level V
CC
= Min, I
OL
= Max
0.35 0.5
Output Voltage V
IL
= Max, V
IH
= Min V
I
OL
= 4 mA, V
CC
= Min 0.25 0.4
I
I
Input Current @ Max V
CC
= Max J, K 0.1
Input Voltage V
I
= 7V Clear 0.3 mA
Clock 0.4
I
IH
HIGH Level V
CC
= Max J, K 20
Input Current V
I
= 2.7V Clear 60 µA
Clock 80
I
IL
LOW Level V
CC
= Max J, K −0.4
Input Current V
I
= 0.4V Clear −0.8 mA
Clock −0.8
I
OS
Short Circuit Output Current V
CC
= Max (Note 6) −20 −100 mA
I
CC
Supply Current V
CC
= Max (Note 7) 4 6 mA
From (Input)
R
L
= 2 kΩ
Symbol Parameter
To (Output)
C
L
= 15 pF C
L
= 50 pF Units
Min Max Min Max
f
MAX
Maximum Clock Frequency 30 25 MHz
t
PHL
Propagation Delay Time Clear
20 28 ns
HIGH-to-LOW Level Output to Q
t
PLH
Propagation Delay Time Clear
20 24 ns
LOW-to-HIGH Level Output to Q
t
PLH
Propagation Delay Time Clock to
20 24 ns
LOW-to-HIGH Level Output Q or Q
t
PHL
Propagation Delay Time Clock to
20 28 ns
HIGH-to-LOW Level Output Q or Q
P1-P3P4-P5

DM74LS73AN

Mfr. #:
Buy DM74LS73AN
Manufacturer:
ON Semiconductor / Fairchild
Description:
Flip Flops Dual J-K Flip-Flop
Lifecycle:
New from this manufacturer.
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