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CY2XF24FLXIT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
CY2XF24
Document Number: 001-53146 Rev. *F Page 4 of 17
Functional Description
The CY2XF24 is a PLL-based high-performance clock
generator. It uses an internal crystal oscillator as a reference,
and outputs one differential LVPECL clock. It has an I
2
C bus
serial interface
[1]
, which is used to change the output frequency.
The CY2XF24 comes configured for four different frequencies.
At power-on, the four configurations are transparently loaded
into an internal volatile memory which, in turn, controls the PLL.
You can switch between the four frequencies through the I
2
C
bus. You can also configure the CY2XF24 with new output
frequencies by shifting new data into the internal memory.
Frequency margining is a common application for this feature.
One frequency is used for the standard operating mode of the
device, while additional frequencies are available for margin
testing, either during product development or in-system
manufacturing test.
Note that all configuration changes made using I
2
C are
temporary and are lost when power is removed from the device.
At power-on, the device returns to its original state.
The configuration for a particular frequency is stored in a 6-byte
block of memory, known as a word. The CY2XF24 has four such
words, labeled ‘Frequency Word 0’ through ‘Frequency Word 3’.
An additional register byte contains a 2-bit field, which selects
one of the four frequency words. By writing to this Select Byte,
you can switch back and forth between the four programmed
frequencies. The select byte can be configured to select any of
the four frequency words at power on.
When changing the output frequency, the frequency transition is
not guaranteed to be smooth. There can be frequency
excursions beyond the start frequency and the new frequency.
Glitches and runt pulses are possible, and time must be allowed
for the PLL to relock.
If more than four frequencies are needed, the I
2
C Bus can be
used to change any of the four frequency words. When writing
frequency words through I
2
C, you should not change the
currently selected word. Instead, write one of the three
unselected words before changing the select byte to select that
new word.
Figure 2 shows how the frequency words are arranged and
selected.
Figure 2. Frequency Words
Configuration Software
Cypress provides CyClockWizard™ software that enables users
to create data values for shifting into the frequency words. This
software is required because the algorithm is too complicated to
be described here.
The user specifies the output frequency. The software then
calculates the bit stream for up to four frequency words, as
outlined by the register addresses for each word seen in
Figure 2.
Programming Description
The CY2XF24 is a programmable device. Before being used in
an application, it must be programmed with the output
frequencies and other variables described in Programming
Variables on page 5. Two different device types are available,
each with its own programming flow. They are described in the
following section.
Field-Programmable CY2XF24F
Field programmable devices are shipped unprogrammed and
must be programmed before being installed on a printed circuit
board (PCB). Customers use CyClockWizard™ Software to
specify the device configuration and generate a joint electron
devices engineering council (JEDEC - extension .jed)
programming file. Programming of samples and prototype
quantities is available using the CyClockWizard software along
with a CY3675-CLKMAKER1 CyClockMaker Clock Programmer
Kit with a CY3675-LCC6A socket adapter. Cypress’s value
added distribution partners also provide programming services.
Field programmable devices are designated with an ‘F’ in the
Standard and Application-Specific Factory Configurations
Part Number Output Frequency Frequency Word
RMS Phase Jitter (Random)
Offset Range Jitter (Typical)
CY2XF24LXI625T 78.125 MHz
156.25 MHz
312.50 MHz
625.00 MHz (default)
0
1
2
3
1.875 MHz to 20 MHz
1.875 MHz to 20 MHz
1.875 MHz to 20 MHz
1.875 MHz to 20 MHz
0.37 ps
0.31 ps
0.29 ps
0.31 ps
CY2XF24LXI009T 100 MHz (default)
156.25 MHz
350 MHz
400 MHz
0
1
2
3
12 kHz to 20 MHz
12 kHz to 20 MHz
12 kHz to 20 MHz
12 kHz to 20 MHz
0.85 ps
0.76 ps
0.71 ps
0.69 ps
Note
1. The serial interface is I
2
C Bus compliant, with the following exceptions: SDA input leakage current, SDA input capacitance, SDA and SCLK are clamped
to V
DD
, setup time, and output hold time.
CY2XF24
Document Number: 001-53146 Rev. *F Page 5 of 17
part number. They are intended for quick prototyping and
inventory reduction. The software and programmer kit hardware
can be downloaded from www.cypress.com by clicking the
hyperlinks above.
Factory-Configured CY2XF24
For ready-to-use devices, the CY2XF24 is available with no field
programming required. Pre-configured devices (see Standard
and Application-Specific Factory Configurations) are available
for samples or orders, or a request for a custom configuration
can be made. All requests are submitted to the local Cypress
field application engineer (FAE) or sales representative. After the
request is processed, the user receives a new part number,
samples, and datasheet with the programmed values. This part
number is used for additional sample requests and production
orders. The CY2XF24 is one-time programmable (OTP).
Programming Variables
Output Frequencies
The CY2XF24 is programmed with up to four independent output
frequencies, which are then selected using the I
2
C interface. The
device can synthesize frequencies to a resolution of 1 part per
million (ppm), but the actual accuracy of the output frequency is
limited by the accuracy of the integrated reference crystal.
The CY2XF24 has an output frequency range of 50 MHz to
690 MHz, but the range is not continuous. The CY2XF24 cannot
generate frequencies in the ranges of 521 MHz to 529 MHz, and
596 MHz to 617 MHz.
Industrial versus Commercial Device Performance
Industrial and commercial devices have different internal
crystals. They have a potentially significant impact on
performance levels for applications requiring the lowest possible
phase noise. CyClockWIzard software allows the user to select
between and view the expected performance of both options.
Memory Map
Five fields can be written through the I
2
C bus. Four frequency
words define the output frequency. As shown in Tab le 3, each of
these words is a 6-byte field. When writing to a frequency word,
all six bytes should be written. They may be written either as
individual byte writes, or as a block write. The currently selected
frequency word should not be written to. All four words are
symmetrical, meaning that a 6-byte value that is valid for one
word is also valid for any of the other words, and produce the
same frequency.
The fifth field is the select byte, located at byte address 40h. The
value written into the two least significant bits determines the
active frequency word. The other bits of the byte are reserved
and must be written with the values indicated in the table.
Users should never write to any address other than the 25 bytes
described here.
Serial Interface Protocol and Timing
The CY2XF24 uses pins SDA and SCLK for an I
2
C bus that
operates up to 100 kbits/sec in read or write mode. The
CY2XF24 is always a slave on this bus, meaning that it never
initiates a bus transaction. The basic write protocol is as follows:
Start Bit; 7-bit Device Address (DA); R/W
Bit; Slave Clock
Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit
Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in
MA+2; ACK; and so on, until STOP Bit. The basic serial format
is illustrated in Figure 4 on page 7.
Device Address
The device address is a 7-bit value. The default serial interface
address is 69H.
Data Valid
Data is valid when the clock is HIGH, and may only be
transitioned when the clock is LOW as illustrated in Figure 5 on
page 7.
Data Frame
Every new data frame is indicated by a start and stop sequence,
as illustrated in Figure 6 on page 7.
START sequence - Start frame is indicated by SDA going LOW
when SCLK is HIGH. Every time a start signal is given, the next
8-bit data must be the device address (seven bits) and a R/W
bit,
followed by register address (eight bits) and register data (eight
bits).
STOP sequence - Stop frame is indicated by SDA going HIGH
when SCLK is HIGH. A stop frame frees the bus for writing to
another part on the same bus or writing to another random
register address.
Table 2. Device Programming Variables
Variable
Output frequency 0
Output frequency 1
Output frequency 2
Output frequency 3
Temperature range (commercial or industrial)
Table 3. Frequency Words
Frequency
Word
Byte Addresses
(hex)
Word Select
(Select Byte 40h)
0 10h to 15h 00
1 16h to 1Bh 01
2 1Ch to 21h 10
3 22h to 27h 11
Table 4. Register 40h: Select Byte
Bits
Default
Value
(binary)
Name Description
7:2 000000 Reserved Reserved. Always write this value
1:0 User-
defined
Word
Select
Selects the Frequency Word to
determine the output frequency.
00 selects Word 0; 01 selects
Word 1; 10 selects Word 2; 11
selects Word 3
CY2XF24
Document Number: 001-53146 Rev. *F Page 6 of 17
Acknowledge Pulse
During write mode, the CY2XF24 responds with an
Acknowledge (ACK) pulse after every eight bits. This is
accomplished by pulling the SDA line LOW during the N*9
th
clock
cycle as illustrated in Figure 7 on page 8. (N = the number of
bytes transmitted). After the data packet is sent during read
mode, the master generates the acknowledge.
Write Operations
Writing Individual Bytes
A valid write operation must have a full 8-bit register address
after the device address word from the master, which is followed
by an acknowledge bit from the slave (SDA = 0/LOW). The next
eight bits must contain the data word intended for storage. After
the data word is received, the slave responds with another
acknowledge bit (SDA = 0/LOW), and the master must end the
write sequence with a STOP condition.
Writing Multiple Bytes
To write more than one byte at a time, the master does not end
the write sequence with a stop condition. Instead, the master can
send multiple contiguous bytes of data to be stored. After each
byte, the slave responds with an acknowledge bit, just like after
the first byte, and accept data until the acknowledge bit is
responded to by the STOP condition. When receiving multiple
bytes, the CY2XF24 internally increments the register address.
Read Operations
Read operations are initiated the same way as write operations
except that the R/W bit of the slave address is set to ‘1’ (HIGH).
There are three basic read operations: current address read,
random read, and sequential read.
Current Address Read
The CY2XF24 has an onboard address counter that retains 1
more than the address of the last word access. If the last word
written or read was word ‘n’, then a current address read
operation would return the value stored in location ‘n+1’. When
the CY2XF24 receives the slave address with the R/W bit set to
a ‘1’, the CY2XF24 issues an acknowledge and transmits the
8-bit word. The master device does not acknowledge the
transfer, but does generate a STOP condition, which causes the
CY2XF24 to stop transmission.
Random Read
Through random read operations, the master may access any
memory location. To perform this type of read operation, first the
word address must be set. This is accomplished by sending the
address to the CY2XF24 as part of a write operation. After the
word address is sent, the master generates a START condition
following the acknowledge. This terminates the write operation
before any data is stored in the address, but not before the
internal address pointer is set. Next the master reissues the
control byte with the R/W byte set to ‘1’. The CY2XF24 then
issues an acknowledge and transmits the 8-bit word. The master
device does not acknowledge the transfer, but does generate a
STOP condition which causes the CY2XF24 to stop
transmission.
Sequential Read
Sequential read operations follow the same process as random
reads except that the master issues an acknowledge instead of
a STOP condition after transmission of the first 8-bit data word.
This action results in an incrementing of the internal address
pointer, and subsequently output of the next 8-bit data word. By
continuing to issue acknowledges instead of STOP conditions,
the master may serially read the entire contents of the slave
device memory. When the internal address pointer points to the
FFh register, after the next increment, the pointer points to the
00h register.
Figure 3. Data Transfer Sequence on the Serial Bus
SCLK
START
Condition
SDA
STOP
Data may Address or
Acknowledge
Valid
be changed
Condition
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

CY2XF24FLXIT

Mfr. #:
Buy CY2XF24FLXIT
Manufacturer:
Cypress Semiconductor
Description:
Phase Locked Loops - PLL HI PERFORMANCE LVPECL OSCILLATOR
Lifecycle:
New from this manufacturer.
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