REV. B
–2–
AD7524–SPECIFICATIONS
Limit, T
A
= +258C Limit, T
MIN
, T
MAX
1
Parameter V
DD
= +5 V V
DD
= +15 V V
DD
= 5 V V
DD
= +15 V Units Test Conditions/Comments
STATIC PERFORMANCE
Resolution 8 8 8 8 Bits
Relative Accuracy
J, A, S Versions ±1/2 ±1/2 ±1/2 ±1/2 LSB max
K, B, T Versions ±1/2 ±1/4 ±1/2 ±1/4 LSB max
L, C, U Versions ±1/2 ±1/8 ±1/2 ±1/8 LSB max
Monotonicity Guaranteed Guaranteed Guaranteed Guaranteed
Gain Error
2
±2 1/2 ±1 1/4 ±3 1/2 ±1 1/2 LSB max
Average Gain TC
3
±40 ±10 ±40 ±10 ppm/°C Gain TC Measured from +25°C to
T
MIN
or from +25°C to T
MAX
DC Supply Rejection,
3
∆Gain/∆V
DD
0.08 0.02 0.16 0.04 % FSR/% max ∆V
DD
= ±10%
0.002 0.001 0.01 0.005 % FSR/% typ
Output Leakage Current
I
OUT1
(Pin 1) ±50 ±50 ±400 ±200 nA max DB0–DB7 = 0 V; WR, CS = 0 V; V
REF
= ±10 V
I
OUT2
(Pin 2) ±50 ±50 ±400 ±200 nA max DB0–DB7 = V
DD
; WR, CS = 0 V; V
REF
= ±10 V
DYNAMIC PERFORMANCE
Output Current Settling Time
3
(to 1/2 LSB) 400 250 500 350 ns max OUT1 Load = 100 Ω, C
EXT
= 13 pF; WR, CS =
0 V; DB0–DB7 = 0 V to V
DD
to 0 V.
AC Feedthrough
3
at OUT1 0.25 0.25 0.5 0.5 % FSR max V
REF
= ±10 V, 100 kHz Sine Wave; DB0–DB7 =
at OUT2 0.25 0.25 0.5 0.5 % FSR max 0 V; WR, CS = 0 V
REFERENCE INPUT
R
IN
(Pin 15 to GND)
4
5555 kΩ min
20 20 20 20 kΩ max
ANALOG OUTPUTS
Output Capacitance
3
C
OUT1
(Pin 1) 120 120 120 120 pF max DB0–DB7 = V
DD
; WR, CS = 0 V
C
OUT2
(Pin 2) 30 30 30 30 pF max
C
OUT1
(Pin 1) 30 30 30 30 pF max DB0–DB7 = 0 V; WR, CS = 0 V
C
OUT2
(Pin 2) 120 120 120 120 pF max
DIGITAL INPUTS
Input HIGH Voltage Requirement
V
IH
+2.4 +13.5 +2.4 +13.5 V min
Input LOW Voltage Requirement
V
IL
+0.8 +1.5 +0.5 +1.5 V max
Input Current
I
IN
±1 ±1 ±10 ±10 µA max V
IN
= 0 V or V
DD
Input Capacitance
3
DB0–DB7 5 5 5 5 pF max V
IN
= 0 V
WR, CS 20 20 20 20 pF max V
IN
= 0 V
SWITCHING CHARACTERISTICS
Chip Select to Write Setup Time
5
See Timing Diagram
t
CS
t
WR
= t
CS
AD7524J, K, L, A, B, C 170 100 220 130 ns min
AD7524S, T, U 170 100 240 150 ns min
Chip Select to Write Hold Time
t
CH
All Grades 0 0 0 0 ns min
Write Pulse Width
t
WR
t
CS
≥ t
WR
, t
CH
≥ 0
AD7524J, K, L, A, B, C 170 100 220 130 ns min
AD7524S, T, U 170 100 240 150 ns min
Data Setup Time
t
DS
AD7524J, K, L, A, B, C 135 60 170 80 ns min
AD7524S, T, U 135 60 170 100 ns min
Data Hold Time
t
DH
All Grades 10 10 10 10 ns min
POWER SUPPLY
I
DD
1 2 2 2 mA max All Digital Inputs V
IL
or V
IH
100 100 500 500 µA max All Digital Inputs 0 V or V
DD
NOTES
1
Temperature ranges as follows: J, K, L versions: –40°C to +85°C
A, B, C versions: –40°C to +85°C
S, T, U versions: –55°C to +125°C
2
Gain error is measured using internal feedback resistor. Full-Scale Range (FSR) = V
REF
.
3
Guaranteed not tested.
4
DAC thin-film resistor temperature coefficient is approximately –300 ppm/°C.
5
AC parameter, sample tested @ +25°C to ensure conformance to specification.
Specifications subje
ct to change without notice
.
(V
REF
= +10 V, V
OUT1
= V
OUT2
= 0 V, unless otherwise noted)
