MAX1515
Low-Voltage, Internal Switch,
Step-Down/DDR Regulator
______________________________________________________________________________________ 19
While sourcing current, V
CHG
and V
DISCHG
increase
with source load current and the voltage across the
inductor decreases. This causes the frequency to drop.
Conversely, while sinking current, V
CHG
and V
DISCHG
decrease with sink load current and the voltage across
the inductor increases. Approximate the change in fre-
quency with the following formula:
where R
DROP
is the resistance of the internal MOSFETs
(40mΩ typ) and the inductor.
Inductor Selection
The key inductor parameters must be specified: induc-
tor value (L) and peak current (I
PEAK
). The following
equation includes a constant, denoted as LIR, which is
the ratio of peak-to-peak inductor AC ripple current to
maximum DC load current. A higher value of LIR allows
smaller inductance but results in higher losses and rip-
ple. A good compromise between size and losses is
found at approximately a 25% ripple-current to load-
current ratio (LIR = 0.25), which corresponds to a peak
inductor current 1.125 times the DC load current:
Additionally, the minimum inductance chosen must be
high enough to limit the inductor current during the
high-side switch on-time to less than 1A/µs.
The peak-inductor current at full load is 1.125 x
I
OUT(MAX)
if the above equation is used; otherwise, the
peak current is calculated by:
Choose an inductor with a saturation current at least as
high as the peak-inductor current. The inductor select-
ed should exhibit low losses at the chosen operating
frequency.
Input Capacitor Selection
The input-filter capacitors reduce peak currents and
noise at the voltage source. Place a low-ESR and low-
ESL 0.1µF capacitor for noise filtering no further than
5mm from IN. Select the bulk input capacitor according
to the RMS input ripple-current requirements and volt-
age rating:
Output Capacitor Selection
The output filter capacitor affects the output-voltage
ripple, output load-transient response, and feedback-
loop stability. For stable operation, the MAX1515
requires a minimum output ripple voltage of V
RIPPLE
1% x V
OUT
. The minimum ESR of the output capacitor
is calculated by:
Stable operation for source-only applications requires
the correct output filter capacitor. When choosing the
output capacitor, ensure that:
For DDR applications, the output capacitance require-
ment needs to be two times the above requirement.
The output filter capacitor must have low enough equiv-
alent series resistance (ESR) to meet output ripple and
load-transient requirements, yet have high enough ESR
to satisfy stability requirements.
For applications where the output is subject to violent
load transients, the output capacitor’s size depends on
how much ESR is needed to prevent the output from
dipping too low under a load transient. Ignoring the sag
due to finite capacitance:
In applications without large and fast load transients,
the output capacitor’s size often depends on how much
ESR is needed to maintain an acceptable level of out-
put voltage ripple. The output ripple voltage of a step-
down controller equals the total inductor ripple current
multiplied by the output capacitor’s ESR. Therefore, the
maximum ESR required to meet ripple specifications is:
R
V
I LIR
ESR
RIPPLE
OUT MAX
()
R
V
I
ESR
STEP
OUT MAX
()
Δ
C
Vt
V
Fs
OUT
REFIN OFF
OUT
×
× /105μμ
ESR
L
t
OFF
% ≥×1
II
VVV
V
RMS OUT MAX
OUT IN OUT
IN
=
()
()
II
Vt
L
PEAK OUT MAX
OUT OFF
=+
×
×
()
2
LV V
s
A
MIN IN MAX OUT
()
()
×
1
1
μ
L
Vt
I LIR
OUT OFF
OUT MAX
=
×
×
()
Δf
IR
Vt
PWM
OUT DROP
IN OFF
=
×
×
MAX1515
Low-Voltage, Internal Switch,
Step-Down/DDR Regulator
20 ______________________________________________________________________________________
The actual capacitance value required relates to the
physical size needed to achieve low ESR, as well as to
the chemistry of the capacitor technology. Thus, the
capacitor is usually selected by ESR and voltage rating
rather than by capacitance value (this is true of tanta-
lums, OS-CONs, polymers, and other electrolytics).
Transient Response
The inductor ripple current also impacts transient-
response performance, especially at low V
IN
- V
OUT
dif-
ferentials. Low inductor values allow the inductor
current to slew faster, replenishing charge removed
from the output filter capacitors by a sudden load step.
The worst-case output sag can be calculated from:
where ΔI
OUT
is the maximum load transient.
Typically, the maximum load transient is equal to the
maximum load current (ΔI
OUT
= I
LOAD(MAX)
). For DDR-
termination applications, the output must source and
sink current. In these applications, the actual peak-to-
peak transient current (ΔI
OUT
) is defined as the sum of
both the maximum source and sink load currents:
The amount of overshoot during a full-load to no-load
transient due to stored inductor energy can be calculat-
ed as:
When using the pulse-skipping source/sink feature
(MODE = V
CC
and SKIP = GND), the output transient
voltage should not exceed or drop below the sink and
source (respectively) detection thresholds (V
REFIN
±20mV).
Applications Information
Dropout Operation
The MAX1515 improves dropout performance by hav-
ing a maximum on-time of 10µs. When working with low
input voltages, the duty-factor limit must be calculated
using worst-case values for on- and off-times. Keep in
mind that transient-response performance of step-down
regulators operated too close to dropout is poor, and
bulk output capacitance must often be added (see the
V
SAG
equation in the Design Procedure section).
The absolute point of dropout is when the inductor cur-
rent ramps down during the off-time (ΔI
DOWN
) as much
as it ramps up during the on-time (ΔI
UP
). The ratio h =
ΔI
UP
/ΔI
DOWN
indicates the controller’s ability to slew
the inductor current higher in response to increased
load, and must always be greater than 1. As h
approaches 1, the absolute minimum dropout point, the
inductor current cannot increase as much during each
switching cycle and V
SAG
greatly increases unless
additional output capacitance is used.
A reasonable minimum value for h is 1.5, but adjusting
this up or down allows trade-offs between V
SAG
, output
capacitance, and minimum operating voltage. For a
given value of h, the minimum operating voltage can be
calculated as:
where V
CHG
and V
DISCHG
are the parasitic voltage
drops in the charge and discharge paths (see the
Frequency Variation with Output Current section),
t
ON(MAX)
is from the Electrical Characteristics, and t
OFF
is the programmed off-time. The absolute minimum
input voltage is calculated with h = 1.
If the calculated V
IN(MIN)
is greater than the required
minimum input voltage, then t
OFF
must be reduced or
output capacitance added to obtain an acceptable
V
SAG
. If operation near dropout is anticipated, calcu-
late V
SAG
to be sure of adequate transient response.
Dropout Design Example:
V
OUT
= 2.5V
t
OFF
= 1µs
V
CHG
= V
DISCHG
= 100mV
h = 1.5
= 2.99V
Dynamic Output-Voltage Transitions
By changing the voltage at REFIN, the MAX1515 can
be used in applications that require dynamic output-
voltage changes between two set points. An n-channel
MOSFET can be used to dynamically adjust the second
controller’s output voltage by changing the resistive
VVV
sVV
s
IN MIN()
..
.(..)
=++
×× +
25 01
15 1 25 01
10
μ
μ
VVV
ht V V
t
IN MIN OUT CHG
OFF OUT DISCHG
ON MAX
()
()
()
=++
×× +
V
IL
CV
SOAR
OUT
OUT OUT
()
Δ
2
2
ΔII I
OUT SOURCE MAX SINK MAX
=+
() ()
V
ILVt
LC V V
Vt
LC
It
C
SAG
OUT OUT OFF
OUT IN OUT
OUT OFF
OUT
OUT OFF
OUT
+
×−
()
+
×
+
()
Δ
Δ
2
2
2
2
MAX1515
Low-Voltage, Internal Switch,
Step-Down/DDR Regulator
______________________________________________________________________________________ 21
voltage-divider network at REFIN. The resulting output
voltages are determined by the following equations:
Forced-PWM operation is required to ensure fast, accu-
rate negative voltage transitions when REFIN is low-
ered. Since forced-PWM operation disables the
zero-crossing comparator, the inductor current can
reverse under light loads, quickly discharging the out-
put capacitors.
For a step voltage change at REFIN, the rate-of-change
of the output voltage is limited by the inductor current
ramp, the total output capacitance, the current limit,
and the load during the transition. The inductor current
ramp is limited by the voltage across the inductor and
the inductance. The total output capacitance deter-
mines how much current is needed to change the out-
put voltage. Additional load current slows down the
output-voltage change during a positive REFIN voltage
change, and speeds up the output-voltage change dur-
ing a negative REFIN voltage change. Increasing the
current-limit setting speeds up a positive output-voltage
change.
To avoid tripping the power-good comparators, the ref-
erence-voltage slew rate must be slow enough that the
output voltage (V
OUT
) can accurately track the refer-
ence voltage (V
REFIN
). Add a capacitor across REFIN
and GND to control the rate-of-change of the REFIN
voltage during dynamic transitions and filter noise.
With the additional capacitance, the REFIN voltage
slews between the two set points with a time constant
given by R
EQ
x C
REFIN
, where R
EQ
is the equivalent
parallel resistance seen by the slew capacitor.
Referring to Figure 7, the time constant for a positive
REFIN voltage transition is:
and the time constant for a negative REFIN voltage
transition is:
PC Board Layout Guidelines
Good layout is necessary to achieve the intended out-
put power level, high efficiency, and low noise. Good
layout includes the use of a ground plane, careful com-
ponent placement, and correct routing of traces using
appropriate trace widths. Refer to the MAX1515 EV kit
for a reference of a good layout.
The following points are in order of decreasing impor-
tance:
1) Minimize switched-current and high-current ground
loops. Connect the input capacitor’s ground, the
output capacitor’s ground, and PGND at a single
point. Connect the resulting island to GND at only
one point.
2) Connect the input filter capacitor less than 5mm
away from IN. The connecting copper trace carries
large currents and must be at least 1mm wide,
preferably 2.5mm.
3) Place the LX node components as close together
and as near to the device as possible. This reduces
noise, resistive losses, and switching losses.
4) A ground plane is essential for optimal perfor-
mance. In most applications, the circuit is located
on a multilayer board, and full use of the four or
more layers is recommended. Use the top and bot-
tom layers for interconnections and the inner layers
for an uninterrupted ground plane. Avoid large AC
currents through the ground plane.
Chip Information
TRANSISTOR COUNT: 8258
PROCESS: BiCMOS
τ
POS REFIN
RR
RR
C=
×
+
12
12
τ
POS REFIN
RRR
RR R
C=
×+
++
123
12 3
()
VV
R
RR
VV
RR
RR R
OUT LOW REF
OUT HIGH REF
()
()
=
+
=
+
++
2
12
23
12 3
MAX1515
LX
GND
FB
PGND
V
OUT
FBSEL1
SKIP
FBSEL0
MODE
REFIN
REF
R3
R2
R1
V
OUT(LOW)
V
OUT(HIGH)
C
OUT
V
CC
L
C
REFIN
Figure 7. Dynamic Output Voltages

MAX1515ETG+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Switching Voltage Regulators 3A 1MHz Step-Down DDR Regulator
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet