PCA9541_7 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 7.1 — 24 June 2015 11 of 42
NXP Semiconductors
PCA9541
2-to-1 I
2
C-bus master selector with interrupt logic and reset
[1] Default values are the same for PCA9541/01 and PCA9541/03.
8.3.2 Register 1: Control Register (B1:B0 = 01b)
The Control Register described below is identical for both the masters. Nevertheless,
there are physically 2 internal Control Registers, one for each upstream channel. When
master 0 reads/writes in this register, the internal Control Register 0 will be accessed.
When master 1 reads/writes in this register, the internal Control Register 1 will be
accessed.
[1] Default values are the same for PCA9541/01 and PCA9541/03.
1 BUSINITMSK R/W 0* After connection is requested and Bus Initialization requested (BUSINIT = 1),
an interrupt on INT will be generated when the bus initialization is done.
Remark: Channel switching is done after bus initialization completed.
1 After connection is requested and Bus Initialization requested (BUSINIT = 1),
an interrupt on INT
will not be generated when the bus initialization is done
(masked).
Remark: Channel switching is done after bus initialization completed.
0 INTINMSK R/W 0* Interrupt on INT_IN will generate an interrupt on INT.
1 Interrupt on INT_IN
will not generate an interrupt on INT (masked)
Table 6. Register 0 - Interrupt Enable (IE) register bit description
…continued
Legend: * default value
Bit Symbol Access Value
[1]
Description
Table 7. Register 1 - Control Register (B1:B0 = 01b) bit allocation
7 6 5 4 3 2 1 0
NTESTON TESTON 0 BUSINIT NBUSON BUSON NMYBUS MYBUS
Table 8. Register 1 - Control Register (B1:B0 = 01b) bit description
Legend: * default value
Bit Symbol Access Value
[1]
Description
7 NTESTON R/W 0* A logic level HIGH to the INT
line of the other channel is sent (interrupt
cleared).
1 A logic level LOW to the INT
line of the other channel is sent (interrupt
generated).
6 TESTON R/W 0* A logic level HIGH to the INT
line is sent (interrupt cleared).
1 A logic level LOW to the INT
line is sent (interrupt generated).
5 - R only 0* not used
4 BUSINIT R/W 0* Bus initialization is not requested.
1 Bus initialization is requested.
3 NBUSON R only see
Table 11
NBUSON bit along with BUSON bit decides whether any upstream channel
is connected to the downstream channel or not. See Table 10
, Table 11, and
Table 12.
2BUSON R/Wsee
Table 11
BUSON bit along with the NBUSON bit decides whether any upstream
channel is connected to the downstream channel or not. See Table 10,
Table 11
, and Table 12.
1 NMYBUS R only see
Table 11
NMYBUS bit along with MYBUS bit decides which upstream channel is
connected to the downstream channel. See Table 9, Table 11, and Table 12.
0 MYBUS R/W see
Table 11
MYBUS bit along with the NMYBUS bit decides which upstream channel is
connected to the downstream channel. See Table 9, Table 11, and Table 12.
