Document Number: 001-09880 Rev. *N Page 7 of 18
Switching Characteristics
Over the Operating Range
Parameter
[17, 18]
Description
55 ns
Unit
Min Max
Read Cycle
t
RC
Read cycle time 55 – ns
t
AA
Address to data valid – 55 ns
t
OHA
Data hold from address change 6 – ns
t
ACE
CE
1
LOW and CE
2
HIGH to data valid – 55 ns
t
DOE
OE LOW to data valid – 25 ns
t
LZOE
OE LOW to LOW Z
[19]
5 – ns
t
HZOE
OE HIGH to High Z
[19, 20]
– 18 ns
t
LZCE
CE
1
LOW and CE
2
HIGH to Low Z
[19]
10 – ns
t
HZCE
CE
1
HIGH and CE
2
LOW to High Z
[19, 20]
– 18 ns
t
PU
CE
1
LOW and CE
2
HIGH to power up 0 – ns
t
PD
CE
1
HIGH and CE
2
LOW to power down – 55 ns
t
DBE
BLE/BHE LOW to data valid – 55 ns
t
LZBE
BLE/BHE LOW to Low Z
[19]
10 – ns
t
HZBE
BLE/BHE HIGH to HIGH Z
[19, 20]
– 18 ns
Write Cycle
[21, 22]
t
WC
Write cycle time 55 – ns
t
SCE
CE
1
LOW and CE
2
HIGH
to write end 40 – ns
t
AW
Address setup to write end 40 – ns
t
HA
Address hold from write end 0 – ns
t
SA
Address setup to write start 0 – ns
t
PWE
WE pulse width 40 – ns
t
BW
BLE/BHE LOW to write end 40 – ns
t
SD
Data setup to write end 25 – ns
t
HD
Data hold from Write End 0 – ns
t
HZWE
WE LOW to High Z
[19, 20]
– 20 ns
t
LZWE
WE HIGH to Low Z
[19]
10 – ns
Notes
17. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the byte enable and/or chip enable
signals as described in the Application Note AN66311. However, the issue has been fixed and in production now, and hence, this Application Note is no longer
applicable. It is available for download on our website as it contains information on the date code of the parts, beyond which the fix has been in production.
18. Test conditions for all parameters other than tristate parameters assume signal transition time of 1 V/ns, timing reference levels of V
CC(typ)
/2, input pulse levels of 0
to V
CC(typ)
, and output loading of the specified I
OL
/I
OH
as shown in Figure 3 on page 5.
19. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given
device.
20. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high impedence state.
21. The internal Write time of the memory is defined by the overlap of WE
, CE
1
= V
IL
, BHE and/or BLE = V
IL
, and CE
2
= V
IH
. All signals must be ACTIVE to initiate a write
and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates
the write.
22. The minimum write pulse width for Write Cycle No. 3 (WE
Controlled, OE LOW) should be sum of t
SD
and t
HZWE
.
