Document Number: 001-09880 Rev. *N Page 4 of 18
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Supply voltage
to ground potential
[4, 5]
...............–0.3 V to V
CC(max)
+ 0.3 V
DC voltage applied to outputs
in High Z state
[4, 5]
......................–0.3 V to V
CC(max)
+ 0.3 V
DC input voltage
[4, 5]
...................–0.3 V to V
CC(max)
+ 0.3 V
Output current into outputs (LOW) .............................20 mA
Static discharge voltage
(per MIL-STD-883, method 3015) ......................... > 2001 V
Latch up current .....................................................> 200 mA
Operating Range
Device Range
Ambient
Temperature
V
CC
[6]
CY62177EV30LL Industrial –40 °C to +85 °C 2.2 V to 3.7 V
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions
55 ns
Unit
Min Typ
[7]
Max
V
OH
Output HIGH voltage I
OH
= –0.1 mA V
CC
= 2.20 V 2.0 – – V
I
OH
= –1.0 mA V
CC
= 2.70 V 2.4 – – V
V
OL
Output LOW voltage I
OL
= 0.1 mA V
CC
= 2.20 V – – 0.4 V
I
OL
= 2.1 mA V
CC
= 2.70 V – – 0.4 V
V
IH
Input HIGH voltage V
CC
= 2.2 V to 2.7 V 1.8 – V
CC
+ 0.3 V
V
CC
= 2.7 V to 3.7 V 2.2 – V
CC
+ 0.3 V
V
IL
Input LOW voltage V
CC
= 2.2 V to 2.7 V –0.3 – 0.6 V
V
CC
= 2.7 V to 3.7 V –0.3 – 0.7
[8]
V
I
IX
Input leakage current GND < V
I
< V
CC
–1 – +1 A
I
OZ
Output leakage current GND < V
O
< V
CC
, Output Disabled –1 – +1 A
I
CC
V
CC
operating supply current f = f
Max
= 1/t
RC
V
CC
= V
CC(max)
I
OUT
= 0 mA
CMOS levels
–3545mA
f = 1 MHz – 4.5 5.5 mA
I
SB2
[9, 10]
Automatic CE power down
current – CMOS inputs
CE
1
> V
CC
– 0.2 V or CE
2
< 0.2 V or
(BHE
and BLE) > V
CC
– 0.2 V,
V
IN
> V
CC
– 0.2 V or V
IN
< 0.2 V, f = 0,
V
CC
= 3.7 V
–325A
Notes
4. V
IL(min)
= –2.0 V for pulse durations less than 20 ns.
5. V
IH(max)
= V
CC
+ 0.75 V for pulse durations less than 20 ns.
6. Full Device AC operation assumes a 100 s ramp time from 0 to V
CC
(min) and 200 s wait time after V
CC
stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25 °C.
8. Under DC conditions the device meets a V
IL
of 0.8 V. However, in dynamic conditions Input LOW Voltage applied to the device must not be higher than 0.7 V.
9. The BYTE
pin in the 48-pin TSOP I package has to be tied to V
CC
to use the device as a 2 M × 16 SRAM.
The 48-pin TSOP I package can also be used as a 4 M × 8 SRAM by tying the BYTE
signal to V
SS
. In the 4 M × 8 configuration, Pin 45 is A21, while BHE, BLE, and
I/O
8
to I/O
14
pins are not used.
10. Chip enables (CE
1
and CE
2
), BYTE, and Byte Enables (BHE and BLE) need to be tied to CMOS levels to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
