ADSP-21xx
REV.
–31–
TIMING PARAMETERS (ADSP-2101/2105/2111/2115/2161/2163)
Frequency
13 MHz 13.824 MHz 16.67 MHz 20 MHz 25 MHz Dependency
Parameter Min Max Min Max Min Max Min Max Min Max Min Max Unit
Timing Requirement:
t
IFS
IRQx
1
or FI Setup before 34.2 33.1 30 27.5 25 0.25t
CK
+ 15
4
ns
CLKOUT Low
2, 3
t
IFS
IRQx
1
or FI Setup before 37.2 36.1 33 30.5 28 0.25t
CK
+ 18
4
ns
CLKOUT Low (ADSP-2111)
2, 3
t
IFH
IRQx
1
or FI Hold after CLKOUT 19.2 18.1 15 12.5 10 0.25t
CK
ns
High
2, 3
Switching Characteristic:
t
FOH
FO Hold after CLKOUT High
5
00 0000 ns
t
FOD
FO Delay from CLKOUT High 15 15 15 15 12 ns
NOTES
1
IRQx=IRQ0, IRQ1, and IRQ2.
2
If IRQx and FI inputs meet t
IFS
and t
IFH
setup/hold requirements, they will be recognized during the current clock cycle; otherwise they will be recognized
during the following cycle. (Refer to the “Interrupt Controller” section in Chapter 3, Program Control, of the ADSP-2100 Family User’s Manual for further
information on interrupt servicing.)
3
Edge-sensitive interrupts require pulse widths greater than 10 ns. Level-sensitive interrupts must be held low until serviced.
4
t
IFS
(min) = 0.25t
CK
+ 20 ns for ADSP-2101TG-50, ADSP-2101TG/883B-50, ADSP-2111TG-52, and ADSP-2111TG/883B-52 ( Extended Temperature Range
devices).
5
t
FOH
(min) = –5 ns for ADSP-2111TG-52 and ADSP-2111TG/883B-52 (Extended Temperature Range devices).
INTERRUPTS & FLAGS
Figure 30. Interrupts & Flags
CLKOUT
FLAG
OUTPUT(S)
t
FOD
IRQx
FI
t
FOH
t
IFH
t
IFS
C
ADSP-21xx
–32–
REV.
Frequency
13 MHz 13.824 MHz 16.67 MHz 20 MHz 25 MHz Dependency
Parameter Min Max Min Max Min Max Min Max Min Max Min Max Unit
Timing Requirement:
t
BH
BR Hold after CLKOUT High
1
24.2 23.1 20 17.5 15 0.25t
CK
+ 5 ns
t
BS
BR Setup before CLKOUT Low
1
39.2 38.1 35 32.5 30 0.25t
CK
+ 20 ns
Switching Characteristic:
t
SD
CLKOUT High to DMS, 39.2 38.1 35 32.5 30 0.25t
CK
+ 20 ns
PMS, BMS, RD, WR Disable
t
SDB
DMS, PMS, BMS, RD, WR00 0 000 ns
Disable to
BG Low
t
SE
BG High to DMS, PMS, 0 0 0 0 0 0 ns
BMS, RD, WR Enable
t
SEC
DMS, PMS, BMS, RD, WR 9.2 8.1 5 2.5 1.5
2
0.25t
CK
– 10
2
ns
Enable to CLKOUT High
NOTES
1
If BR meets the t
BS
and t
BH
setup/hold requirements, it will be recognized in the current processor cycle; otherwise it is recognized in the following cycle. BR requires
a pulse width greater than 10 ns.
2
For 25 MHz only the minimum frequency dependency formula for t
SEC
= (0.25t
CK
– 8.5).
Section 10.2.4, “Bus Request/Grant,” on page 212 of the ADSP-2100 Family User’s Manual (1st Edition, 1993) states that “When BR is recognized, the processor
responds immediately by asserting BG during the same cycle.” This is incorrect for the current versions of all ADSP-21xx processors: BG is asserted in the cycle after
BR is recognized. No external synchronization circuit is needed when BR is generated as an asynchronous signal.
TIMING PARAMETERS (ADSP-2101/2105/2111/2115/2161/2163)
BUS REQUEST/GRANT
CLKOUT
PMS, DMS
BMS, RD
WR
t
BS
BR
BG
CLKOUT
t
SD
t
SDB
t
SE
t
SEC
t
BH
Figure 31. Bus Request/Grant
C
ADSP-21xx
REV.
–33–
Frequency Dependency
(CLKIN 25 MHz)
Parameter Min Max Unit
Timing Requirement:
t
RDD
RD Low to Data Valid 0.5t
CK
– 13 + w ns
t
AA
A0–A13, PMS, DMS, BMS to Data Valid 0.75t
CK
– 18 + w ns
t
RDH
Data Hold from RD High 0
Switching Characteristic:
t
RP
RD Pulse Width 0.5t
CK
– 8 + w ns
t
CRD
CLKOUT High to RD Low 0.25t
CK
– 5 0.25t
CK
+ 10 ns
t
ASR
A0–A13, PMS, DMS, BMS Setup before
RD Low 0.25t
CK
– 10
1
ns
t
RDA
A0–A13, PMS, DMS, BMS Hold after RD
Deasserted 0.25t
CK
– 9 ns
t
RWR
RD High to RD or WR Low 0.5t
CK
– 5 ns
NOTES
1
For 25 MHz only minimum frequency dependency formula for t
ASR
= (0.25t
CK
– 8.5).
w = wait states × t
CK.
TIMING PARAMETERS (ADSP-2101/2105/2111/2115/2161/2163)
MEMORY READ
Figure 32. Memory Read
CLKOUT
A0 – A13
D
t
RDA
RD
WR
DMS, PMS
BMS
t
RWR
t
RP
t
ASR
t
CRD
t
RDD
t
AA
t
RDH
13 MHz 13.824 MHz 16.67 MHz 20 MHz 25 MHz
Parameter Min Max Min Max Min Max Min Max Min Max Unit
Timing Requirement:
t
RDD
RD Low to Data Valid 23.5 23.2 17 12 7 ns
t
AA
A0–A13, PMS, DMS, BMS to Data Valid 37.7 36.2 27 19.5 12 ns
t
RDH
Data Hold from RD High 0 0 0 0 0 ns
Switching Characteristic:
t
RP
RD Pulse Width 33.5 28.2 22 17 12 ns
t
CRD
CLKOUT High to RD Low 14.2 29.2 13.1 28.1 10 25 7.5 22.5 5 20 ns
t
ASR
A0–A13, PMS, DMS, BMS Setup before 9.2 8.1 5 2.5 1.5
1
ns
RD Low
t
RDA
A0–A13, PMS, DMS, BMS Hold after RD 10.2 9.1 6 3.5 1 ns
Deasserted
t
RWR
RD High to RD or WR Low 33.5 31.2 25 20 15 ns
C

ADSP-2105BP-80

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital Signal Processors & Controllers - DSP, DSC 16-Bit 20 MIPS 5V 1 Serial Port
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union