2 Electrical characteristics STF8NK100Z - STP8NK100Z
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Table 6. Switching times
Table 7. Source drain diode
Table 8. Gate-source zener diode
(1) Limited only by maximum temperature allowed
(2)I
SD
≤ 6.5 A, di/dt ≤ 200A/µs, V
DS
≤ V
(BR)DSS,
Tj≤ Tjmax
(3) Pulse width limited by safe operating area
(4) The built-in-back-to-back Zener diodes have specifically been designed to enanche not only the device’s ESD capability, but
also to make them safely absorb possible voltage is appropriate to archieve an efficient and cost-effective intervention to
protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components.
(5) C
oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C
oss
when V
DS
increases from 0
to 80% V
DSS
(6) Pulsed: pulse duartion = 300µs, duty cycle 1.5%
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(on)
t
r
Turn-on Delay Time
Rise Time
V
DD
=500 V, I
D
= 3.15 A,
R
G
=4.7Ω, V
GS
=10V
(see Figure 18)
28
19
ns
ns
t
d(off)
t
f
Turn-off Delay Time
FallTime
V
DD
=500 V, I
D
=3.15 A,
R
G
=4.7Ω, V
GS
=10V
(see Figure 18)
59
30
ns
ns
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
Note 3
Source-drain Current
Source-drain Current (pulsed)
6.5
26
A
A
V
SD
Note 2
Forward on Voltage
I
SD
=6.3A, V
GS
=0
1.6 V
t
rr
Q
rr
I
RRM
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
SD
=6.3A, di/dt = 100A/µs,
V
DD
=50 V, Tj=25°C
620
5.3
17
ns
µC
A
t
rr
Q
rr
I
RRM
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
SD
=6.3A, di/dt = 100A/µs,
V
DD
=50 V, Tj=150°C
840
7.5
18
ns
µC
A
Symbol Parameter Test Conditions Min. Typ. Max. Unit
BV
GSO
Note 4
Gate-Source Breakdown
Voltage
Igs = ± 1mA (Open Drain) 30 V
