MC100EP140DG

© Semiconductor Components Industries, LLC, 2006
November, 2006 Rev. 9
1 Publication Order Number:
MC100EP140/D
MC100EP140
3.3VECL Phase−Frequency
Detector
Description
The MC100EP140 is a three state phase frequencydetector
intended for phaselocked loop applications which require a minimum
amount of phase and frequency difference at lock. Since the part is
designed with fully differential internal gates, the noise is reduced
throughout the circuit, especially at high speeds. The basic operation
of a Phase/Frequency Detector (PFD) is to “compare” an incoming
signal (feedback) to a set reference signal. When the Reference (R)
and Feedback (FB) inputs are unequal in frequency and/or phase, the
differential UP (U) and DOWN (D) outputs will provide pulse streams
which, when subtracted and integrated, provide an error voltage for
control of a VCO. Detector states of operation are shown in the
Figure 2 and the State Table.
The typical output amplitude of the EP140 is 400 mV, allowing
faster switching time and greater bandwidth. For proper operation, the
input edge rate of the R and FB inputs should be less than 5 ns.
More information on Phase Lock Loop operation and application
can be found in AND8040.
The pinout is shown in Figure 1, the logic diagram in Figure 3, and
the typical termination in Figure 5.
Features
500 ps Typical Propagation Delay
Maximum Frequency > 2.1 GHz Typical
Fully Differential Internally
Advanced High Band Output Swing of 400 mV
Transfer Gain: 1.0 mV/Degree at 1.4 GHz
1.2 mV/Degree at 1.0 GHz
Rise and Fall Time: 100 ps Typical
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: V
CC
= 3.0 V to 3.6 V
with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
= 3.0 V to 3.6 V
Open Input Default State
PbFree Packages are Available
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
SOIC8
D SUFFIX
CASE 751
MARKING DIAGRAMS*
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
1
8
KP140
ALYW
G
1
8
MC100EP140
http://onsemi.com
2
Figure 1. 8Lead Pinout (Top View)
Figure 2. Phase Detector Logic Model
8
1
V
CC
U
7
2
R
U
6
3
FB
D
5
4
V
EE
D
Table 1. PIN DESCRIPTION
PIN
D, D
U, U Differential Up Outputs
FUNCTION
Differential Down Outputs
V
CC
V
EE
Negative Supply
Positive Supply
FB* ECL Feedback Input
R* ECL Reference Input
Table 2. STATE TABLE
PHASE
DETECTOR
STATE
INPUT OUTPUT
PUMP DOWN
212
RFB UD
PUMP UP
232
2
21
12
2
2
23
32
2
L
L
H
L
L
H
L
L
L
L
L
L
L
H
L
L
L
H
H
L
L
L
H
L
L
H
L
L
L
L
L
L
* Pins will default LOW when left open.
3
U = H
D = L
1 2
U = L
D = H
U = L
D = L
Pump
Down
Pump
Up
FB
FB FB
RR
R
Figure 3. Logic Diagram
U
R
U
U
A
FB
D
B
B
A
Reset
Reset
C
D
A
C
D
B
Reset
Reset
C
A
B
D
D
D
S
R
FF
U
R
S
FF
D
V
EE
MC100EP140
http://onsemi.com
3
Table 3. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor
37.5 kW
ESD Protection Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg PbFree Pkg
SOIC8 Level 1 Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 @ 0.125 in
Transistor Count 457 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
PECL Mode Power Supply V
EE
= 0 V 6 V
V
EE
NECL Mode Power Supply V
CC
= 0 V 6 V
V
I
PECL Mode Input Voltage
NECL Mode Input Voltage
V
EE
= 0 V
V
CC
= 0 V
V
I
v V
CC
V
I
w V
EE
6
6
V
V
I
out
Output Current Continuous
Surge
50
100
mA
mA
T
A
Operating Temperature Range 40 to +85 °C
T
stg
Storage Temperature Range 65 to +150 °C
q
JA
Thermal Resistance (JunctiontoAmbient) 0 lfpm
500 lfpm
SOIC8
SOIC8
190
130
°C/W
°C/W
q
JC
Thermal Resistance (JunctiontoCase) Standard Board SOIC8 41 to 44 °C/W
T
sol
Wave Solder Pb
PbFree
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 5. 100EP DC CHARACTERISTICS, PECL V
CC
= 3.3 V, V
EE
= 0 V (Note 2)
40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
I
EE
Power Supply Current 45 65 85 50 70 90 53 73 93 mA
V
OH
Output HIGH Voltage (Note 3) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV
V
OL
Output LOW Voltage (Note 3) 1755 1880 2005 1755 1880 2005 1755 1880 2005 mV
V
IH
Input HIGH Voltage (SingleEnded) 2075 2420 2075 2420 2075 2420 mV
V
IL
Input LOW Voltage (SingleEnded) 1355 1675 1355 1675 1355 1675 mV
I
IH
Input HIGH Current 150 150 150
mA
I
IL
Input LOW Current 0.5 0.5 0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.3 V to 0.3 V.
3. All loading with 50 W to V
CC
2.0 V.

MC100EP140DG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Phase Detectors / Shifters 3.3V ELC Phase Freq. Detector
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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