LTC2913
9
2913fb
UV/OV Timing
The LTC2913 has an adjustable timeout period (t
UOTO
) that
holds OV or UV asserted after all faults have cleared. This
assures a minimum reset pulse width allowing a settling
time delay for the monitored voltage after it has entered
the valid region of operation.
When any VH input drops below its designed threshold,
the UV pin asserts low. When all inputs recover above
their designed thresholds, the UV output timer starts. If
all inputs remain above their designed thresholds when
the timer fi nishes, the UV pin weakly pulls high. However,
if any input falls below its designed threshold during this
timeout period, the timer resets and restarts when all inputs
are above the designed thresholds. The OV output behaves
as the UV output when LATCH is high (LTC2913-1).
Selecting the UV/OV Timing Capacitor
The UV and OV timeout period (t
UOTO
) for the LTC2913
is adjustable to accommodate a variety of applications.
Connecting a capacitor, C
TMR
, between the TMR pin and
ground sets the timeout period. The value of capacitor
needed for a particular timeout period is:
C
TMR
= t
UOTO
• 115 • 10
–9
[F/s]
The Reset Timeout Period vs Capacitance graph found in
the Typical Performance Characteristics shows the desired
delay time as a function of the value of the timer capacitor
that must be used. The TMR pin must have a minimum
10pF load or be tied to V
CC
. For long timeout periods, the
only limitation is the availability of a large value capacitor
with low leakage. Capacitor leakage current must not exceed
the minimum TMR charging current of 1.3μA. Tying the
TMR pin to V
CC
will bypass the timeout period.
Undervoltage Lockout
When V
CC
falls below 2V, the LTC2913 asserts an
undervoltage lockout (UVLO) condition. During UVLO,
UV is asserted and pulled low while OV is cleared and
blocked from asserting. When V
CC
rises above 2V, UV
follows the same timing procedure as an undervoltage
condition on any input.
Shunt Regulator
The LTC2913 has an internal shunt regulator. The V
CC
pin
operates as a direct supply input for voltages up to 6V.
Under this condition, the quiescent current of the device
remains below a maximum of 80μA. For V
CC
voltages higher
than 6V, the device operates as a shunt regulator and must
have a resistance R
Z
between the supply and the V
CC
pin
to limit the current to no greater than 10mA.
When choosing this resistance value, select an appropriate
location on the I-V curve shown in the Typical Performance
Characteristics to accommodate any variations in V
CC
due
to changes in current through R
Z
.
UV and OV Output Characteristics
The DC characteristics of the UV and 0V pull-down strength
are shown in the Typical Performance Characteristics. Each
pin has a weak internal pull-up to V
CC
and a strong pull-
down to ground. This arrangement allows these pins to
have open-drain behavior while possessing several other
benefi cial characteristics. The weak pull-up eliminates the
need for an external pull-up resistor when the rise time on
the pin is not critical. On the other hand, the open-drain
confi guration allows for wired-OR connections, and is
useful when more than one signal needs to pull down
on the output. V
CC
of 1V guarantees a maximum V
OL
=
0.15V at UV.
At V
CC
= 1V, the weak pull-up current on OV is barely turned
on. Therefore, an external pull-up resistor of no more than
100k is recommended on the OV pin if the state and pull-up
strength of the OV pin is crucial at very low V
CC
.
Note however, by adding an external pull-up resistor, the
pull-up strength on the OV pin is increased. Therefore, if
it is connected in a wired-OR connection, the pull-down
strength of any single device must accommodate this
additional pull-up strength.
Output Rise and Fall Time Estimation
The UV and OV outputs have strong pull-down capabil-
ity. The following formula estimates the output fall time
(90% to 10%) for a particular external load capacitance
(C
LOAD
):
t
FALL
≈ 2.2 • R
PD
• C
LOAD
APPLICATIONS INFORMATION
