70914S25PFGI

6.42
IDT70914S
High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
10
Truth Table II: Clock Enable Function Table
(1)
Truth Table I: Read/Write Control
(1)
Functional Description
The IDT70914 provides a true synchronous Dual-Port Static RAM
interface. Registered inputs provide very short set-up and hold times on
address, data, and all critical control inputs. All internal registers are clocked
on the rising edge of the clock signal. An asynchronous output enable is
provided to ease asynchronous bus interfacing.
The internal write pulse width is dependent on the LOW to HIGH
transitions of the clock signal allowing the shortest possible realized cycle
times. Clock enable inputs are provided to stall the operation of the address
and data input registers without introducing clock skew for very fast
interleaved memory applications.
A HIGH on the CE input for one clock cycle will power down the
internal circuitry to reduce static power consumption.
NOTES:
1. 'H' = HIGH voltage level steady state, 'h' = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition, 'L' = LOW voltage level steady state 'l' = LOW
voltage level one set-up time prior to the LOW-to-HIGH clock transition, 'X' = Don't care, 'NC' = No change
2. CLKEN = V
IL must be clocked in during Power-Up.
3. Control signals are initialted and terminated on the rising edge of the CLK, depending on their input level. When R/W and CE are LOW, a write cycle is initiated on
the LOW-to-HIGH transition of the CLK. Termination of a write cycle is done on the next LOW-to-HIGH transistion of the CLK.
4. The register outputs are internal signals from the register inputs being clocked in or disabled by CLKEN.
Mode
Inputs Register Inputs Register Outputs
(4 )
CLK
(3 )
CLKEN
(2 )
ADDR DATAIN ADDR DATAOUT
Load "1"
LHHHH
Load "0"
LLLLL
Hold (do nothing)
HXXNCNC
X H X X NC NC
3490 tbl 10
Inputs
Outputs
Mode
Synchronous
(3)
Asynchronous
CLK
CE
R/W
OE
I/O
0-8
H X X High-Z Deselected, Power-Down
LL X DATA
IN
Selected and Write Enabled
LH L DATA
OUT
Read Selected and Data Output Enable Read
X X H High-Z Outputs Disabled
3490 tbl 09
6.42
IDT70914S
High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
11
Ordering Information
NOTE:
1. Industrial temperature range is available on selected TQFP packages in standard power.
For specific speeds, packages and powers contact your sales office.
XXXX A 999 A A
Device
Type
Power Speed Package Process/
Temperature
Range
Blank
I
(1)
B
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Military (-55°C to +85°C)
Compliant to MIL-PRF-38535 QML
J
PF
68-pin PLCC (J68-1)
80-pin TQFP (PN80-1)
12
15
20
25
Commercial Only
Commercial Only
Commercial & Military
Military Only
S
Standard Power
70914
36K (4K x 9-Bit) Synchronous Dual-Port RAM
3490 drw 12
Speed in nanoseconds
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
3/10/99: Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Page 2 and 3 Added additional notes to pin configurations
6/7/99: Changed drawing format
11/10/99: Replaced IDT logo
5/24/00: Page 4 Increased storage temperature parameter
Clarified TA parameter
Page 5 DC Electrical parameters–changed wording from "open" to "disabled"
Changed ±200mV to 0mV in notes
1/12/01: Removed PGA pinout (obsolete package)
Changed cycle time of 12ns part from 17ns (58MHz) to 16ns (60MHz)
10/21/08: Page 11 Removed "IDT" from orderable part number
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794
San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com
www.idt.com

70914S25PFGI

Mfr. #:
Manufacturer:
Description:
IC SRAM 36K PARALLEL 80TQFP
Lifecycle:
New from this manufacturer.
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