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AT45DB081B-CI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33
13
AT45DB081B
2225F–DFLSH–5/03
AC Characteristics
Symbol Parameter
AT45DB081B
(2.5V Version) AT45DB081B
UnitsMin Max Min Max
f
SCK
SCK Frequency 15 20 MHz
f
CAR
SCK Frequency for Continuous Array Read 15 20 MHz
t
WH
SCK High Time 30 22 ns
t
WL
SCK Low Time 30 22 ns
t
CS
Minimum CS High Time 250 250 ns
t
CSS
CS Setup Time 250 250 ns
t
CSH
CS Hold Time 250 250 ns
t
CSB
CS High to RDY/BUSY Low 200 200 ns
t
SU
Data In Setup Time 10 5 ns
t
H
Data In Hold Time 15 10 ns
t
HO
Output Hold Time 0 0 ns
t
DIS
Output Disable Time 20 18 ns
t
V
Output Valid 25 20 ns
t
XFR
Page to Buffer Transfer/Compare Time 300 250 µs
t
EP
Page Erase and Programming Time 20 20 ms
t
P
Page Programming Time 14 14 ms
t
PE
Page Erase Time 8 8 ms
t
BE
Block Erase Time 12 12 ms
t
RST
RESET Pulse Width 10 10 µs
t
REC
RESET Recovery Time 1 1 µs
14
AT45DB081B
2225F–DFLSH–5/03
Input Test Waveforms and Measurement Levels
t
R
, t
F
< 3 ns (10% to 90%)
Output Test Load
AC Waveforms
Two different timing diagrams are shown below. Waveform 1 shows the SCK signal
being low when CS
makes a high-to-low transition, and Waveform 2 shows the SCK sig-
nal being high when CS
makes a high-to-low transition. Both waveforms show valid
timing diagrams. The setup and hold times for the SI signal are referenced to the low-to-
high transition on the SCK signal.
Waveform 1 shows timing that is also compatible with SPI Mode 0, and Waveform 2
shows timing that is compatible with SPI Mode 3.
Waveform 1 – Inactive Clock Polarity Low and SPI Mode 0
Waveform 2 – Inactive Clock Polarity High and SPI Mode 3
AC
DRIVING
LEVELS
AC
MEASUREMENT
LEVEL
0.45V
2.0
0.8
2.4V
DEVICE
UNDER
TEST
30 pF
CS
SCK
SI
SO
t
CSS
VALID IN
t
H
t
SU
t
WH
t
WL
t
CSH
t
CS
t
V
HIGH IMPEDANCE
VALID OUT
t
HO
t
DIS
HIGH IMPEDANCE
CS
SCK
SI
SO
t
CSS
VALID IN
t
H
t
SU
t
WL
t
WH
t
CSH
t
CS
t
V
HIGH Z
VALID OUT
t
HO
t
DIS
HIGH IMPEDANCE
15
AT45DB081B
2225F–DFLSH–5/03
Reset Timing (Inactive Clock Polarity Low Shown)
Note: The CS signal should be in the high state before the RESET signal is deasserted.
Command Sequence for Read/Write Operations (except Status Register Read)
Notes: 1. “r” designates bits reserved for larger densities.
2. It is recommended that “r” be a logical “0” for densities of 8M bits or smaller.
3. For densities larger than 8M bits, the “r” bits become the most significant Page Address bit for the appropriate density.
CS
SCK
RESET
SO
HIGH IMPEDANCE HIGH IMPEDANCE
SI
t
RST
t
REC
t
CSS
SI CMD 8 bits
8 bits
8 bits
MSB
Reserved for
larger densities
Page Address
(PA11-PA0)
Byte/Buffer Address
(BA8-BA0/BFA8-BFA0)
LSBr r r X X X X X X X X X X X X X X X X X X X X X
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33

AT45DB081B-CI

Mfr. #:
Buy AT45DB081B-CI
Manufacturer:
Microchip Technology / Atmel
Description:
NOR Flash 8M bit
Lifecycle:
New from this manufacturer.
Delivery:
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