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PSMN040-200W,127

P1-P3P4-P6P7-P7
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PSMN040-200W
FEATURES SYMBOL QUICK REFERENCE DATA
• ’Trench’ technology
• Very low on-state resistance V
DSS
= 200 V
• Fast switching
• Low thermal resistance I
D
= 50 A
R
DS(ON)
≤ 40 mΩ
GENERAL DESCRIPTION PINNING SOT429 (TO247)
SiliconMAXproductsuse thelatest PIN DESCRIPTION
Philips Trench technology to
achieve the lowest possible 1 gate
on-state resistance in each
package at each voltage rating. 2 drain
Applications:- 3 source
• d.c. to d.c. converters
• switched mode power supplies tab drain
The PSMN040-200W is supplied in
the SOT429 (TO247) conventional
leaded package.
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DSS
Drain-source voltage T
j
= 25 ˚C to 175˚C - 200 V
V
DGR
Drain-gate voltage T
j
= 25 ˚C to 175˚C; R
GS
= 20 kΩ - 200 V
V
GS
Gate-source voltage - ± 20 V
I
D
Continuous drain current T
mb
= 25 ˚C - 50 A
T
mb
= 100 ˚C - 36 A
I
DM
Pulsed drain current T
mb
= 25 ˚C - 200 A
P
D
Total power dissipation T
mb
= 25 ˚C - 300 W
T
j
, T
stg
Operating junction and - 55 175 ˚C
storage temperature
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
E
AS
Non-repetitive avalanche Unclamped inductive load, I
AS
= 50 A; - 661 mJ
energy t
p
= 100 µs; T
j
prior to avalanche = 25˚C;
V
DD
≤ 25 V; R
GS
= 50 Ω; V
GS
= 10 V; refer
to fig:15
I
AS
Non-repetitive avalanche - 50 A
current
d
g
s
2
3
1
August 1999 1 Rev 1.000
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PSMN040-200W
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
R
th j-mb
Thermal resistance junction - 0.5 K/W
to mounting base
R
th j-a
Thermal resistance junction in free air 45 - K/W
to ambient
ELECTRICAL CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
(BR)DSS
Drain-source breakdown V
GS
= 0 V; I
D
= 0.25 mA; 200 - - V
voltage T
j
= -55˚C 178 - - V
V
GS(TO)
Gate threshold voltage V
DS
= V
GS
; I
D
= 1 mA 2.0 3.0 4.0 V
T
j
= 175˚C 1.0 - - V
T
j
= -55˚C - - 6 V
R
DS(ON)
Drain-source on-state V
GS
= 10 V; I
D
= 25 A - 35 40 mΩ
resistance T
j
= 175˚C - - 116 mΩ
I
GSS
Gate source leakage current V
GS
= ±10 V; V
DS
= 0 V - 2 100 nA
I
DSS
Zero gate voltage drain V
DS
= 200 V; V
GS
= 0 V; - 0.05 10 µA
current T
j
= 175˚C - - 500 µA
Q
g(tot)
Total gate charge I
D
= 50 A; V
DD
= 160 V; V
GS
= 10 V - 183 - nC
Q
gs
Gate-source charge - 40 - nC
Q
gd
Gate-drain (Miller) charge - 73 - nC
t
d on
Turn-on delay time V
DD
= 100 V; R
D
= 3.9 Ω; - 43 - ns
t
r
Turn-on rise time V
GS
= 10 V; R
G
= 5.6 Ω -94-ns
t
d off
Turn-off delay time Resistive load - 230 - ns
t
f
Turn-off fall time - 92 - ns
L
d
Internal drain inductance Measured from tab to centre of die - 3.5 - nH
L
d
Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH
L
s
Internal source inductance Measured from source lead to source - 7.5 - nH
bond pad
C
iss
Input capacitance V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz - 9530 - pF
C
oss
Output capacitance - 732 - pF
C
rss
Feedback capacitance - 380 - pF
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
I
S
Continuous source current - - 50 A
(body diode)
I
SM
Pulsed source current (body - - 200 A
diode)
V
SD
Diode forward voltage I
F
= 25 A; V
GS
= 0 V - 0.85 1.2 V
t
rr
Reverse recovery time I
F
= 20 A; -dI
F
/dt = 100 A/µs; - 160 - ns
Q
rr
Reverse recovery charge V
GS
= 0 V; V
R
= 30 V - 1.4 - µC
August 1999 2 Rev 1.000
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PSMN040-200W
Fig.1. Normalised power dissipation.
PD% = 100
⋅
P
D
/P
D 25 ˚C
= f(T
mb
)
Fig.2. Normalised continuous drain current.
ID% = 100
⋅
I
D
/I
D 25 ˚C
= f(T
mb
); V
GS
≥
10 V
Fig.3. Safe operating area
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
Fig.5. Typical output characteristics, T
j
= 25 ˚C
.
I
D
= f(V
DS
)
Fig.6. Typical on-state resistance, T
j
= 25 ˚C
.
R
DS(ON)
= f(I
D
)
Normalised Power Derating, PD (%)
0
10
20
30
40
50
60
70
80
90
100
0 25 50 75 100 125 150 175
Mounting Base temperature, Tmb (C)
0.001
0.01
0.1
1
1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00
Pulse width, tp (s)
Transient thermal impedance, Zth j-mb (K/W)
single pulse
D = 0.5
0.2
0.1
0.05
0.02
tp
D = tp/T
D
P
T
Normalised Current Derating, ID (%)
0
10
20
30
40
50
60
70
80
90
100
0 25 50 75 100 125 150 175
Mounting Base temperature, Tmb (C)
0
5
10
15
20
25
30
35
40
45
50
55
60
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Drain-Source Voltage, VDS (V)
Drain Current, ID (A)
4.4 V
Tj = 25 C
VGS = 10V
4.6 V
4.8 V
5 V
8 V
4.2 V
6 V
1
10
100
1000
1 10 100 1000
Drain-Source Voltage, VDS (V)
Peak Pulsed Drain Current, IDM (A)
D.C.
100 ms
10 ms
RDS(on) = VDS/ ID
1 ms
tp = 10 us
100 us
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
0.18
0.2
0 5 10 15 20 25 30 35 40
Drain Current, ID (A)
Drain-Source On Resistance, RDS(on) (Ohms)
VGS = 10V
Tj = 25 C
6V
4.8 V
5 V
4.6 V
4.4 V
4.2 V
August 1999 3 Rev 1.000
P1-P3P4-P6P7-P7

PSMN040-200W,127

Mfr. #:
Buy PSMN040-200W,127
Manufacturer:
NXP Semiconductors
Description:
MOSFET N-CH 200V 50A SOT429
Lifecycle:
New from this manufacturer.
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