ADG3257
Rev. E | Page 3 of 12
SPECIFICATIONS
V
CC
= 5.0 V ± 10%, GND = 0 V. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
1
Symbol Conditions
2
B Version
Unit Min Typ
3
Max
DC ELECTRICAL CHARACTERISTICS
Input High Voltage V
INH
2.4 V
Input Low Voltage V
INL
−0.3 +0.8 V
Input Leakage Current I
I
0 ≤ V
IN
≤ 5.5 V ±0.01 ±1 μA
Off State Leakage Current I
OZ
0 ≤ A, B ≤ V
CC
±0.01 ±1 μA
On State Leakage Current I
OZ
0 ≤ A, B ≤ V
CC
±0.01 ±1 μA
Maximum Pass Voltage
4
V
P
V
IN
= V
CC
= 5 V, I
O
= −5 μA 3.9 4.2 4.4 V
CAPACITANCE
4
A Port Off Capacitance C
A
OFF f = 1 MHz 7 pF
B Port Off Capacitance C
B
OFF f = 1 MHz 5 pF
A, B Port On Capacitance C
A
, C
B
ON f = 1 MHz 11 pF
Control Input Capacitance C
IN
f = 1 MHz 4 pF
SWITCHING CHARACTERISTICS
4
Propagation Delay A to B or B to A, t
PD
t
PHL
, t
PLH
5
V
A
= 0 V, C
L
= 50 pF 0.10 ns
Propagation Delay Matching
6
V
A
= 0 V, C
L
= 50 pF 0.0075 0.035 ns
Bus Enable Time BE to A or B
t
PZH
, t
PZL
C
L
= 50 pF, R
L
= 500 Ω 1 5 7.5 ns
Bus Disable Time BE to A or B
t
PHZ
, t
PLZ
C
L
= 50 pF, R
L
= 500 Ω 1 3.5 7 ns
Bus Select Time S to A or B
Enable t
SEL_EN
C
L
= 50 pF, R
L
= 500 Ω 8 12 ns
Disable t
SEL_DIS
C
L
= 50 pF, R
L
= 500 Ω 5 8 ns
Maximum Data Rate V
A
= 2 V p-p 933 Mbps
DIGITAL SWITCH
On Resistance R
ON
V
A
= 0 V
I
O
= 48 mA, 15 mA, 8 mA, T
A
= 25°C 2 4 Ω
I
O
= 48 mA, 15 mA, 8 mA 5 Ω
V
A
= 2.4 V
I
O
= 48 mA, 15 mA, 8 mA, T
A
= 25°C 3 6 Ω
I
O
= 48 mA, 15 mA, 8 mA 7 Ω
On-Resistance Matching ΔR
ON
V
A
= 0 V, I
O
= 48 mA, 15 mA, 8 mA 0.15 Ω
POWER REQUIREMENTS
V
CC
3.0 5.5 V
Quiescent Power Supply Current I
CC
Digital inputs = 0 V or V
CC
0.001 1 μA
Increase in I
CC
per Input
4, 7
ΔI
CC
V
CC
= 5.5 V, one input at 3.0 V; others at V
CC
or GND 200 μA
1
Temperature range is: Version B: –40°C to +85°C.
2
See Test Circuits section.
3
All typical values are at T
A
= 25°C, unless otherwise noted.
4
Guaranteed by design, not subject to production test.
5
The digital switch contributes no propagation delay other than the RC delay of the typical R
ON
of the switch and the load capacitance when driven by an ideal voltage
source. Because the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation
delay of the digital switch, when used in a system, is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
6
Propagation delay matching between channels is calculated from on-resistance matching of worst-case channel combinations and load capacitance.
7
This current applies to the control pins only and represents the current required to switch internal capacitance at the specified frequency. The A and B ports contribute
no significant ac or dc currents as they transition.
